hdlverifier.VivadoHDLCosimulation

Create a System object for HDL cosimulation with the Vivado simulator and MATLAB

Since R2022a

Description

The hdlverifier.VivadoHDLCosimulation System object™ cosimulates MATLAB^® and a hardware component using the Vivado^® simulator. The system object writes input signals to and reads output signals from an HDL model under simulation in the HDL simulator. You can use this System object to model a source or sink device by configuring the System object with only output or input ports, respectively.

To create a System object for HDL cosimulation with MATLAB:

1. Create a customized hdlverifier.VivadoHDLCosimulation object using Cosimulation Wizard.

2. Assign the object to a variable in your design.

3. Call the object with arguments, as if it were a function.

To learn more about how System objects work, see What Are System Objects?.

Creation

To create an hdlverifier.VivadoHDLCosimulation System object, you must first use the Cosimulation Wizard to generate a customized VivadoHDLCosimulation System object. The output of the Cosimulation Wizard is a file called hdlcosim_toplevel.m, where toplevel is the name of the top level HDL module. You can then create the System object by assigning it to a local variable.

Syntax

hdlc = hdlcosim_topLevel

Description

hdlc = hdlcosim_topLevel creates an hdlverifier.VivadoHDLCosimulation System object, where topLevel is the name of your top level HDL module. The properties of this System object are configured by the Cosimulation Wizard. This System object provides an interface to your HDL simulation in your MATLAB workspace.

hdlcosim_toplevel is created and configured with the Cosimulation Wizard, and that is the recommended syntax to use.

After assigning the object to a variable, you can change properties by assigning a value to it. For example, to change the fraction length value:

hdlc = hdlcosim_myTopLevel;
hdlc.OutputFractionLengths = 10;

The Cosimulation Wizard creates an hdlverifier.VivadoHDLCosimulation System object using existing HDL code, and an HDL launch script. Use the Cosimulation Wizard for easy startup.

Properties

Unless otherwise indicated, properties are nontunable, which means you cannot change their values after calling the object. Objects lock when you call them, and the release function unlocks them.

If a property is tunable, you can change its value at any time.

For more information on changing property values, see System Design in MATLAB Using System Objects.

Note that only the following properties can be changed: OutputSigned, OutputDataTypes, OutputFractionLengths, ClockResetTypes, ClockResetTimes, PreRunTime, SampleTime. Other properties should only be configured with the Cosimulation Wizard.

InputSignals — Input paths in HDL code

'' (default) | string | character vector | cell array of character vectors

This property is read-only.

Input paths in the HDL code, specified as a string, character vector, or cell array of character vectors. The paths are specified relative to the top level of the HDL hierarchy.

Example: 'data_in'

Example: {'/top/in1','/top/in2'}

Data Types: char | cell | string

OutputSignals — Output paths in HDL code

'' (default) | string | character vector | cell array of character vectors

This property is read-only.

Output paths in the HDL code, specified as a string, character vector, or cell array of character vectors. The paths are specified relative to the top level of the HDL hierarchy.

Example: 'out1'

Example: {'out1','out2'}

Data Types: char | cell | string

OutputDataTypes — Data types of output signals

'' (default) | 'fixedpoint' | 'double' | 'single'

Data types of the output signals, specified as a cell array of character vectors. Valid data types are 'fixedpoint','double', or 'single'.

If you specify only one data type, each output has that same data type. To assign different data types to each output, specify a cell array of the same size as the number of outputs. Each element in the OutputDataTypes cell array specifies the data type of the corresponding element in the System object output (hdloutputs).

Example: {'fixedpoint'} – All output data types are fixedpoint.

Example: {'double','single'} – The data type of the first output is double and the second is single.

Note

When OutputDataTypes is {'fixedpoint'}, the bit-width matches the size of a built-in data type (8,16,32, or 64), and OutputFractionLengths is set to 0, the data type of the output signal is returned as that built-in data type.

Data Types: cell

OutputSigned — Sign of outputs

false (default) | true | logical vector

Sign of the outputs, specified as false (unsigned), true (signed), or a logical vector.

If you provide only true or false, each output has that corresponding sign. To apply different signs to each output, specify a logical vector of the same size as the number of outputs. Each element in the OutputSigned vector specifies the sign of the corresponding element in the System object output (hdloutputs).

Example: true – All outputs have a signed value.

Example: [true,true,false] — The first output is a signed value, the second output is a signed value, and the third (and final) output is an unsigned value.

OutputFractionLengths — Output fraction lengths

0 (default) | integer | vector of integers

Output fraction lengths, in bits, specified as an integer or vector of integers.

If you specify only a scalar, each output has that same fraction length. To apply different fraction lengths to each output, specify a vector of the same size as the number of outputs. Each element in the OutputFractionLengths vector specifies the fraction length of the corresponding element in the System object output (hdloutputs).

Example: 10 — All outputs have a fraction length of 10 bits.

Example: [16,8] — The first output has a fraction length of 16 bits, and the second (and final) output has a fraction length of 8 bits.

ClockResetSignals — Clock and reset signals to drive in HDL code

'' (default) | string | character vector | cell array of strings | cell array of character vectors

This property is read-only.

Clock and reset signals to drive in the HDL code, specified as a string or cell array of N strings. Each string contains a path to a clock or reset port in the HDL module.

Example: /inverter/clk

Data Types: char | cell | string

ClockResetTypes — Clock and reset waveform types to generate

'' (default) | string | character vector | cell array of strings | cell array of character vectors

Clock and reset waveform types to generate, specified as a string or cell array of strings. Each string contains a clock or reset type, corresponding to the list specified in the ClockResetSignals property. The following values are valid clock and reset types:

• 'Active Rising Edge Clock'

• 'Active Falling Edge Clock'

• 'Step 0 to 1'

• 'Step 1 to 0'

Example: Active Rising Edge Clock

Data Types: char | cell | string

ClockResetTimes — HDL times for clock period or step function duration

{ } (default) | cell array of positive integer and time unit | cell array of cell arrays

HDL times for clock period or step function duration, specified as a cell array of a positive integer and a time unit. Valid values for time units are:

• 'fs' — Femtoseconds

• 'ps' — Picoseconds

• 'ns' — Nanoseconds

• 'us' — Microseconds

• 'ms' — Milliseconds

• 's' — Seconds

To specify multiple clocks or step functions, use a cell array of cell arrays corresponding to the list specified in the ClockResetSignals property.

Example: {10,'ps'} specifies a single clock or step function with a 10 picosecond duration.

Example: {{10,'ns'}, {8,'ps'}} specifies two clocks, one with a 10 nanosecond duration and one with an 8 picosecond duration.

Data Types: cell

PreRunTime — Delay in HDL simulator before cosimulation

{0,'ns'} (default) | cell array

Delay in HDL simulator before the cosimulation starts, specified as a cell array with two elements.

• The first element is the HDL presimulation delay, specified as a nonnegative integer.

• The second element is the time unit, specified as one of these character vectors: 'fs','ps','ns','us','ms', or 's'.

Example: {10,'fs'}

Data Types: cell

SampleTime — Elapsed simulator time between calls to the System object

{10,'ns'} (default) | cell array

Elapsed time in the HDL simulator between each call to the System object, specified as a cell array with two elements.

• The first element is the time between two calls to the System object, specified as a positive integer.

• The second element is the time unit, specified as a character vector: 'fs','ps','ns','us','ms','s'.

Example: {10,'ns'}

Data Types: cell

XSIData — Data structure that matches the cosimulation interface to vivadosimlib.slx library

struct

This property is read-only.

Data structure matching the cosimulation interface to the vivadosimlib.slx library, specified as an XsiData struct. Create this struct by invoking the Cosimulation Wizard and customize your design for Vivado cosimulation. XSIData includes the following fields:

• ProductName — 'EDA Simulator Link VS'

• DesignLib — Path to the dynamic link library (DLL) file.

• Language — HDL language, where 0 indicates Verilog and 1 indicates VHDL

• TimePrecision — HDL time precision, in seconds, specified as the exponent. For example, a time precision of one picosecond is equivalent to 10^(-12) seconds, is specified as -12

• HdlSigInfo — A struct that contains the dimensions and type of all inputs and outputs

• ResetInfo — A struct that contains the name, initial value, and duration of the reset signal

Note

The information in this struct is read-only. To change any of the fields in this struct, rerun the Cosimulation Wizard tool.

Example: xsiData = struct with fields: ProductName: 'EDA Simulator Link VS' DesignLib: 'xsim.dir/design/xsimk' Language: 1 TimePrecision: -12 HdlSigInfo: [1×2 struct] ResetInfo: [0×0 struct]

Data Types: struct

Usage

Syntax

hdloutputs = hdlc(hdlinputs)

Description

hdloutputs = hdlc(hdlinputs) connects to the HDL simulator, writes hdlinputs to the HDL simulator, and reads hdloutputs from the HDL simulator. The elapsed simulation time between each call to the System object is defined by the SampleTime property.

Input Arguments

hdlinputs — Inputs to HDL simulator

comma-separated list of values for HDL input ports

Inputs to the HDL simulator, specified as a comma-separated list of values that are driven to your HDL input ports. The HDL input ports are set by the InputSignals property. The number of elements in this comma-separated pair must equal the number of HDL input ports. Each input argument value is driven to its corresponding HDL input port.

For example, if InputSignals is set as {'in1','in2'}, specify out = hdlc(input1,input2) to drive the value input1 to in1 and input2 to in2.

Example: [RealFft, ImagFft] = hdlc(3,12); the values 3 and 12 are driven as inputs to the HDL simulator, which has two input ports.

Output Arguments

hdloutputs — Outputs from the HDL simulator

scalar | vector

Outputs from the HDL simulator, returned as a scalar or vector. Each returned element is the output from its corresponding HDL output port. The HDL output ports are specified in the OutputSignals property. The number of elements returned is the same as the number of HDL output ports specified. For example, if OutputSignals is set as {'out1','out2'}, specify [o1, o2] = hdlc(i1,i2) to assign the value from out1 to o1 and out2 to o2.

Example: out1 = hdlc(3,12); assigns the output value from an HDL simulator with one output port.

Example: [RealFft, ImagFft] = hdlc(3,12); assigns output values from an HDL simulator with two output ports. In this example, RealFft is the output from the first port and ImagFft is the output from the second port.

Object Functions

To use an object function, specify the System object as the first input argument. For example, to release system resources of a System object named obj, use this syntax:

release(obj)

Common to All System Objects

step	Run System object algorithm
release	Release resources and allow changes to System object property values and input characteristics
reset	Reset internal states of System object

Examples

Cosimulation Wizard for MATLAB System Object

Set up an HDL Verifier™ application using the Cosimulation Wizard.

This example uses a MATLAB® System object™ and following HDL simulators to verify a register transfer level (RTL) design.

• Vivado® Simulator from AMD®

• ModelSim™ or Questa™ from Siemens EDA

• Xcelium® from Cadence®

The example design is a Fast Fourier Transform (FFT) of size 8 written in Verilog. The FFT is commonly used in digital signal processing applications to produce frequency distribution of a signal.

To verify the correctness of this FFT, a MATLAB System object testbench is provided. This testbench generates a periodic sinusoidal input to the HDL design under test (DUT) and plots the Fourier Coefficients in the Complex Plane.

The Cosimulation Wizard takes the provided Verilog file of this FFT as its input. It also collects user input required for setting up cosimulation in each step. At the end of the example, the Cosimulation Wizard generates a MATLAB script that instantiates a configured HdlCosimulation System object, a MATLAB script that compiles HDL design and a MATLAB script that launches the HDL simulator for cosimulation.

1. Launch Cosimulation Wizard

Launch the Cosimulation Wizard tool by executing this command in MATLAB.

cosimWizard

2. Specify Cosimulation Type

On the Cosimulation Type page, perform the following steps:

a. If you are using ModelSim, set HDL Simulator to ModelSim.

If you are using Xcelium, set HDL Simulator to Xcelium.

If you are using Vivado Simulator, set HDL Simulator to Vivado Simulator.

b. Set HDL cosimulation to MATLAB System Object.

c. Do not change the default Use HDL simulator executables on the system path option if the HDL simulator executables appear on your system path. If these executable do not appear on the path, specify the HDL simulator path.

d. Click Next.

3. Select HDL Files

On the HDL Files page, perform the following steps:

a. Add HDL files to the file list:

• Click Add and select the Verilog files fft_hdl.v and fft_hdl_tc.v in your example folder.

• Review the files in the file list to make sure the file type is correctly identified.

b. Click Next.

4. Specify HDL Compilation Commands

The Cosimulation Wizard lists the default commands in the Compilation Commands window. For this example, you do not need to change these commands.

Compilation commands for the ModelSim follow.

Click Next. The MATLAB console displays the compilation log. If an error occurs during compilation, that error appears in the Status area. Correct the error before proceeding to the next step.

5. Select HDL Modules for Cosimulation

On the Simulation Options page, perform the following steps:

a. Specify the name of the HDL module or entity for cosimulation.

For ModelSim or Xcelium

From the list, select fft_hdl. This module is the Verilog module you use for cosimulation. If you do not see fft_hdl in the list, enter the file name manually.

The Simulation options for the ModelSim follow.

For Vivado Simulator

For the Vivado simulator, name of Verilog module is selected by default. The Simulation options for Vivado simulator follow.

b. Click Next. The Cosimulation Wizard launches the HDL simulator in the background console using the specified HDL module and simulation options. When the wizard launches the HDL simulator successfully, the wizard populates the input and output ports on the Verilog model fft_hdl and displays them in the next step.

6. Specify Input/Output Port Types

In this step, the Cosimulation Wizard displays two tables containing the input and output ports of fft_hdl, respectively.

The Cosimulation Wizard attempts to correctly identify the port type for each port. If the wizard incorrectly identifies a port, you can change the port type using these tables.

• For input ports, you can select Clock, Reset, Input, or Unused. HDL Verifier connects only the input ports marked Input to MATLAB during cosimulation.

• HDL Verifier connects output ports marked Output with MATLAB during cosimulation. The link software and MATLAB ignore those output ports marked Unused during cosimulation.

• You can change the parameters for signals identified as Clock and Reset in a later step.

For this example, accept the default port types and click Next.

7. Specify Output Port Details

For this example, the HDL FFT outputs are signed, 13 bits long with 9 bits of fraction length. On the Output Port Details page, perform the following steps:

a. Note that the Sample Time cannot be changed and is always fixed to 1 when you use the HdlCosimulation System object.

b. Set the Data Type to Fixedpoint for both outputs.

c. Set the Sign to Signed for both inputs.

d. Set the Fraction Length to 9 for both outputs.

e. Click Next.

8. Set Clock and Reset Details

Set the clock period (ns) to 20. The Verilog code indicates that the reset is synchronous and the active value is 1. You can reset the entire HDL design at time 1 ns, triggered by the rising edge of the clock. Use a duration of 15 ns for the reset signal. On the Clock/Reset Details page, perform the following steps:

a. Set the clock period to 20.

b. Set the active edge to Rising.

c. Set the reset initial value to 1.

d. Set the reset signal duration to 15.

Click Next.

9. Confirm Start Time Alignment

The Start Time Alignment page displays a plot for the waveforms of clock and reset signals. The Cosimulation Wizard indicates the HDL time to start cosimulation with a red line. The start time is also the time at which the System object gets the first input sample from the HDL simulator. The active edge of the clock is a rising edge. Thus, at time 20 ns in the HDL simulator, the registered output of the FFT is stable. No race condition exists and the default HDL time to start cosimulation (20 ns) is correct.

Click Next.

10. Generate System Object

Before the Cosimulation Wizard generates the scripts, you have the option to modify the HDL Simulator sampling period. The sampling period determines the time in the HDL Simulator that elapses between each call to step in MATLAB. The sampling period is typically equal to the clock period. You can also specify if your inputs and outputs are frame based (instead of sample based).

Click Finish to complete the Cosimulation Wizard session.

11. Create Testbench to Verify HDL Design

For this example, you do not actually create the testbench. Instead, you can find the finished script fft_tb.m in the directory where your verilog files reside.

After you click Finish in the Cosimulation Wizard, the application generates three MATLAB scripts in the current directory.

For ModelSim and Xcelium

• compile_hdl_design_fft_hdl.m: To recompile the HDL design.

• launch_hdl_simulator_fft_hdl.m: Relaunches the MATLAB System object server and starts the HDL simulator.

• hdlcosim_fft_hdl.m: Creates the HdlCosimulation System object.

For Vivado Simulator

• hdlverifier_compile.m: Recompiles the HDL design.

• hdlverifier_gendll_fft_hdl.m: Creates a compiled shared library containing the HDL design and simulation kernel integrated into the behavior of the System object.

• hdlcosim_fft_hdl.m: Creates the HdlCosimulation System object.

Open the files fft_tb.m and hdlcosim_fft_hdl.m, located in the same directory as the Verilog files, and observe the HdlCosimulation System object calls. hdlcosim_fft_hdl.m contains the HdlCosimulation instantiation and fft_tb.m contains a MATLAB System object testbench. Use this testbench to verify the HDL design for the corresponding HdlCosimulation System object.

12. Run Cosimulation and Verify HDL Design

For ModelSim and Xcelium

Launch the HDL simulator by executing the script launch_hdl_simulator_fft_hdl.m.

launch_hdl_simulator_fft_hdl

When the HDL simulator is ready, return to MATLAB and start the simulation by executing the script fft_tb.m.

fft_tb

For Vivado Simulator

Start the simulation by executing the script fft_tb.m.

fft_tb

Verify the result from the plot in the testbench. The plot displays the Fourier coefficients in the complex plane.

See Also

• hdlverifier.HDLCosimulation

• hdlverifier.VivadoHDLCosimulation

• Cosimulation Wizard

Version History

Introduced in R2022a