Sequence Feedback
Add-On Required: This feature requires the ASIC Testbench for HDL Verifier add-on.
Libraries:
HDL Verifier /
For Use with DPI-C SystemVerilog
Description
The Sequence Feedback block promotes a feedback signal from the scoreboard
to the sequence in a UVM testbench model. The block implements a Unit
Delay (Simulink) block with the Initial condition parameter set to
0
.
Ports
Input
Output
Version History
Introduced in R2023a