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UVM Generation

Generate UVM components from Simulink® subsystems

Generate Universal Verification Methodology (UVM) test components and a behavioral design under test (DUT) from a Simulink model. You can use the generated components in two ways.

  • Generate a UVM top model with a test bench and a behavioral (DUT). Use the generated UVM top module as a test environment, and replace the generated behavioral DUT with your own simulation model.

  • Generate UVM test components, and integrate them into your existing UVM environment.

This feature requires Simulink Coder™.


uvmbuildGenerate UVM test bench from Simulink model


Sequence FeedbackConnect between scoreboard and sequence in UVM test bench model


uvmcodegen.uvmconfigUVM configuration object
svdpiConfigurationConfigure workflows for UVM and SystemVerilog component generation from MATLAB