Follow instructions for invoking the HDL Workflow Advisor. See Getting Started with the HDL Workflow Advisor (HDL Coder).
You must have an HDL Coder™ license to generate HDL code using the HDL Workflow Advisor.
At step 1, Set Target, click 1.1 Set Target Device and Synthesis Workflow and do the following:
FPGA-in-the-Loop from the pull-down list at
Under Target Platform, select a development board from the pull-down
list. Family, Device, Package,
and Speed are filled in by the HDL Workflow Advisor. If you have not yet
downloaded an HDL
Verifier™ FPGA board support package, select
Get more boards.
Then return to this step after you have downloaded an FPGA board support package.
For Folder, enter the folder name to save the project files into.
The default is
hdl_prj under the current working folder.
After you select a FIL target in Step 1.1, click 1.2 Set Target Frequency.
Set the Target Frequency (MHz) for the clock speed of your design
implemented on the FPGA. The available range of frequencies is shown in the
Frequency Range (MHz) parameter. For Intel® boards and Xilinx® boards, Workflow Advisor checks the requested frequency against those possible
for the requested board. If the requested frequency is not possible for this board, Workflow
Advisor returns an error and suggests an alternate frequency. For Xilinx
Vivado®-supported boards, or PCI
Express® boards, Workflow Advisor cannot check the frequency. The synthesis tools make a
best effort attempt at the requested frequency but may choose an alternate frequency if the
specified frequency was not achievable. The default is
At step 2, Prepare Model for HDL Code Generation, perform steps 2.1–2.4 as described in Prepare Model For HDL Code Generation Overview (HDL Coder).
In addition, perform step 2.5 Check FPGA-in-the-Loop Compatibility to verify that the model is compatible with FIL.
At step 3, HDL Code Generation, perform steps 3.1 and 3.2 as described in HDL Code Generation Overview (HDL Coder).
At step 4.1, Set FPGA-in-the-Loop Options, change these options if necessary:
FPGA-in-the-Loop Connection: FIL simulation
connection method. The options in the drop-down menu update depending
on the connection methods supported for the target board you selected.
If the target board and HDL
Verifier support the connection, you
When you select an Ethernet connection, you can adjust the board IP and MAC addresses, if necessary.
|Board IP address|
Use this option for setting the IP address of the board if it is not the default IP address (192.168.0.2).
If the default board IP address (192.168.0.2) is in use by another device, or you need a different subnet, change the Board IP address according to the following guidelines:
|Board MAC address|
Under most circumstances, you do not need to change the board MAC address. If you connect more than one FPGA development board to a single host computer, change the board MAC address for any additional boards so that each address is unique. You must have a separate NIC for each board.
To change the Board MAC address, click in the Board MAC address field. Specify an address that is different from that belonging to any other device attached to your computer. To obtain the Board MAC address for a specific FPGA development board, refer to the label affixed to the board or consult the product documentation.
Specify additional source files for the HDL design:
Indicate additional source files for the DUT using Add. To (optionally) display the full paths to the source files, check the box titled Show full paths to source files. The HDL Workflow Advisor attempts to identify the source file type. If the file type is incorrect, you can change it by selecting from the File Type drop-down list.
FIL Over Ethernet
FIL Over JTAG
FIL Over PCI Express
At step 4.2, Build FPGA-in-the-Loop, click Run this task.
During the build process, the following actions occur:
The HDL Workflow Advisor generates a FIL block named after the top-level module and places it in a new model. The next figure shows an example of the new model containing the FIL block.
After new model generation, the HDL Workflow Advisor opens a command window:
In this window, the FPGA design software performs synthesis, fit, PAR, and FPGA programming file generation.
When the process completes, a message in the command window prompts you to close the window.
The HDL Workflow Advisor builds a test bench model around the generated FIL block.
Ensure your FPGA development board is set up, powered on, and connected to your machine as directed by the board manufacturer documentation. Then, perform the following steps to program the FPGA:
Double-click the FIL block in your Simulink® model to open the block mask.
On the Main tab, click Load to download the programming file to the FPGA.
The load process may take several minutes, depending on how large the subsystem is. For very large subsystems, the process can take an hour or longer.
For further troubleshooting tips, see Load Programming File onto FPGA.
In Simulink, on the Simulation tab, click Run. The results of the FIL simulation should match those of the Simulink reference model or of the original HDL code.
Regarding initialization: Simulink starts from time 0 every time, which means the RAM in Simulink is initialized to zero. However, this is not true in hardware. If you have RAM in your design, the first simulation will match Simulink, but any subsequent runs may not match.
The workaround is to reload the FPGA bitstream before re-running the simulation. To do this, click Load on the FIL block mask.