Check Discrete Gradient
Check that absolute value of difference between successive samples of discrete signal is less than specified value
Libraries:
Simulink /
Model Verification
HDL Coder /
Model Verification
Description
The Check Discrete Gradient block checks each signal element and determines
whether the absolute value of the difference between successive values of the element is
less than an specified value. The block then executes an assertion after comparison. You
can specify the value of gradient (1
by default) by adjusting the
Maximum gradient parameter. If the input signal difference is
less than the absolute value of the Maximum gradient, the assertion
is true (1)
and the block does nothing. If not, the block halts the
simulation and returns an error message by default.
Note
To run simulations, the Check Discrete Gradient block requires a fixed-step discrete solver. If another solver is selected, an error prompts.
Examples
Check Signal Slope with Check Discrete Gradient Block
Using the Check Discrete Gradient block, you can check if the absolute value of the difference between successive samples of a signal is less than a defined value.
In this example, the Check Discrete Gradient block compares the value of an input signal from a Sine Wave block to the Maximum gradient parameter value, which is 0.1
. If the absolute value of the difference between successive samples of the signal is less than 0.1
, the block asserts true (1)
. Because the Output assertion signal parameter of the block is selected, the block outputs the assertion value. The block requires a fixed-step discrete solver, which has been selected in the model. Run the simulation to observe the model output.
The block asserts true
when the sine wave is near a maximum or minimum. In these sections of the signal, the absolute value of the gradient is less than the Maximum gradient value 0.1
. This pattern repeats until the simulation end time.
Ports
Input
Port_1 — Input signal checked against gradient
scalar | vector | matrix
Input signal the block checks to determine if the difference of each element between successive samples is less than the absolute value of the Maximum gradient parameter.
Data Types: single
| double
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| fixed point
Output
Port_1 — Assertion output signal
scalar
Output signal that is true (1)
if the assertion succeeds, and
false (0)
if the assertion fails. If, in the
Configuration Parameters window, in the Math and Data
Types section, under Advanced
parameters, you select Implement logic signals
as Boolean data, then the output data type is
Boolean
. Otherwise, the data type of the signal
is double
.
Dependencies
To enable this output port, select the Output assertion signal parameter check box.
Data Types: double
| Boolean
Parameters
Maximum gradient — Maximum value of allowed differences
1
(default) | scalar
Specify the value on the allowed gradient of the input signal.
Programmatic Use
Parameter:
gradient
|
Type: string scalar or character vector |
Values: real scalar |
Default:
"1"
|
Enable assertion — Enable or disable check
on
(default) | off
Clearing this parameter disables the block and causes the model to behave as if the
block does not exist. To enable or disable all verification blocks, regardless of the
setting of this option, go to the Configuration Parameters window, click Diagnostics > Data Validity, expand the Advanced parameters section, and set
Model Verification block enabling to Enable
all
or Disable all
.
Programmatic Use
Parameter:
enabled
|
Type: string scalar or character vector |
Values:
"on" | "off" |
Default:
"on"
|
Simulation callback when assertion fails (optional) — Expression to evaluate when assertion fails
""
(default) | MATLAB expression
Specify a MATLAB® expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.
Dependencies
To enable this parameter, select Enable assertion.
Programmatic Use
Parameter:
callback
|
Type: string scalar or character vector |
Default:
""
|
Stop simulation when assertion fails — Whether to stop simulation when check fails
on
(default) | off
Select this parameter to stop the simulation when the check fails. Clear this parameter to display a warning and continue the simulation.
Programmatic Use
Parameter:
stopWhenAssertionFail
|
Type: string scalar or character vector |
Values:
"on" | "off" |
Default:
"on"
|
Output assertion signal — Create output signal
off
(default) | on
Select this parameter to enable the output port.
Programmatic Use
Parameter:
export
|
Type: string scalar or character vector |
Values:
"on" | "off" |
Default:
"off"
|
Select icon type — Select icon type
graphic
(default) | text
Specify the style of the block icon. The graphic
option displays a
graphical representation of the assertion condition on the icon. The
text
option displays a mathematical expression that represents
the assertion condition.
Programmatic Use
Parameter:
icon
|
Type: string scalar or character vector |
Values:
"graphic" | "text" |
Default:
"graphic"
|
Block Characteristics
Data Types |
|
Direct Feedthrough |
|
Multidimensional Signals |
|
Variable-Size Signals |
|
Zero-Crossing Detection |
|
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
For information about how Simulink® Coder™ generated code handles Model Verification blocks, see Configure Model for Debugging (Simulink Coder).
Not recommended for production code.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
Architecture | Description |
---|---|
No HDL | Do not generate HDL code for this block. |
PreserveUpstreamLogic | Control the removal of unconnected logic. The default
is |
PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.
Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.
Version History
Introduced before R2006a
See Also
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