Identify Automatic Bus Conversions
To comply with composite signal requirements and limitations, the software may add hidden Bus to Vector and Signal Conversion blocks to your model. These additions help you avoid manually converting or refactoring your models, which can be time consuming and error prone.
When a block requires a vector but receives a virtual bus, a hidden Bus to Vector block may convert the bus to a vector. Bus to Vector blocks are virtual and do not affect simulation results, code generation, or performance. However, when a bus is treated as a vector, the elements of the bus become inaccessible.
To receive warnings or errors when a bus is treated as a vector, set the Bus
signal treated as vector configuration parameter to
These settings allow you to identify potential problems at the source, instead of at
downstream blocks that expect a bus.
To correct buses used as vectors:
In the Model Advisor for the top model, run the Check bus signals treated as vectors check and perform the recommended actions.
Simulink.BlockDiagram.addBusToVectorfunction to add Bus To Vector blocks where the software would implicitly convert buses to vectors.
Replace the related Bus Creator block with a Mux block, which creates a vector.
Virtual and Nonvirtual Bus Conversions
When updating a diagram before simulation or code generation, the software might automatically convert a virtual bus to a nonvirtual bus or a nonvirtual bus to a virtual bus. For example, the software implicitly converts a bus when:
A block, such as an S-Function block or a Stateflow® chart, receives a virtual bus but requires a nonvirtual bus.
A referenced model receives a nonvirtual bus, but the corresponding Inport block specifies a virtual bus.
A root-level Outport block receives a nonvirtual bus but specifies a virtual bus.
The software inserts hidden Signal Conversion blocks into the model where
needed. If a
Simulink.Bus object is not specified for a virtual bus, the
conversion to a nonvirtual bus fails, and you receive an error.
Unlike Bus to Vector blocks, Signal Conversion blocks do not affect the structure of the output bus.
By default, In Bus Element and Out Bus Element blocks inherit the bus virtuality from the bus. When they specify either a virtual or nonvirtual bus, they produce an error instead of automatically converting the bus virtuality.