High-Level Synthesis Code Generation
R2026bHigh-Level Synthesis (HLS) enables you to generate C++ code from MATLAB® algorithms and implement those algorithms in hardware. The MATLAB-to-HLS workflow integrates HDL Coder™ with AMD® Vitis® HLS tools, allowing you to generate HLS-compatible code, create IP cores, and deploy them on AMD FPGA and SoC devices.
Use HDL Coder to generate and verify HLS code from MATLAB algorithms. Then use SoC Blockset™ for AMD workflows to package, integrate, and deploy the generated HLS IP on supported AMD hardware platforms.
The AMD Vitis HLS integration workflows require both HDL Coder and SoC Blockset for AMD licenses.
For information about algorithm design, supported MATLAB syntax and functions, code generation, fixed-point conversion, optimization, and HLS verification workflows, see High-Level Synthesis Code Generation (HDL Coder).
Apps
| HDL Coder | Generate HDL and High-Level Synthesis (HLS) code from MATLAB code |
Functions
hdlsetuptoolpath | Set up system environment to access FPGA synthesis software |
hdlsetuphlstoolpath | Set up system environment to access High-Level Synthesis (HLS) software (Since R2022a) |
Topics
- Get Started with HLS IP Core Generation Workflow (HDL Coder)
Generate HLS code and deploy the generated IP core on the ZedBoard hardware.
- Support MATLAB Math Functions for Xilinx Vitis HLS
Support mathematical functions with floating-point types for AMD Vitis HLS. (Since R2026a)
- Deploy HLS IP Core for Image Convolution on Zynq with DDR Access
Generate HLS code and deploy the generated IP core on Zynq with DDR access. (Since R2026a)
Related Information
- High-Level Synthesis Code Generation (HDL Coder)
