visionzynq.downloadImage

Write image to on-board SD card and load into FPGA

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Add-On Required: This feature requires the SoC Blockset Support Package for AMD FPGA and SoC Devices add-on.

Syntax

downloadImage(vz,'FPGAImage')
downloadImage(vz,'FPGAImage',filename)
downloadImage(vz,'FPGAImage',filename,'DTBImage',dtree)

Description

downloadImage(vz,'FPGAImage') writes the default FPGA image, which is located in the support package installation folder, to the SD card of the visionzynq target. The function then loads the image to the FPGA and restarts the board. The function does not return until the board restart is complete. The default FPGA image has pass-through logic in place of the FPGA user logic and uses the Vision HDL Toolbox™ custom pixel-streaming interface.

example

downloadImage(vz,'FPGAImage',filename) downloads a custom FPGA image to the on-board SD card and then loads the image into the FPGA and restarts the board. This syntax is valid only when the FPGA image contains FPGA user logic that has a Vision HDL Toolbox custom pixel-streaming interface.

Use the downloadImage function when the image you want is not yet on the hardware SD card. Use the changeFPGAImage function when the file is already on the SD card.

example

downloadImage(vz,'FPGAImage',filename,'DTBImage',dtree) downloads the specified FPGA image and configures the device tree on the board. The device tree settings must match the interface that the FPGA user logic has: a Vision HDL Toolbox custom pixel-streaming interface or an AXI4-Stream Video interface.

example

Examples

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If you do not have this object defined in the workspace, create an object that contains a connection to the board.

vz = visionzynq

vz = 


visionzynq

   Device Information:
       DeviceName: 'ZC706 FMC-HDMI-CAM'
    DeviceAddress: '192.168.4.2'
         Username: 'root'
         Password: 'root'
             Port: 22

Download the default FPGA image to the Zynq® board.

downloadImage(vz,'FPGAImage')
### ConfiguringFPGA image ...
## Transferring image to hardware SD card:
              DownloadKind: 'FPGAImage'
              DownloadMode: 'interactive'
            DownloadSource: 'C:\ML\SupportPackages\R2021b\toolbox\shared\supportpackages\visionzynq\bin\target\sdcard\visionzynq-zc706-hdmicam\visionzynq-refdes\visionzynq-zc706-hdmicam.bit'
                  DTBImage: 'C:\ML\SupportPackages\R2021b\toolbox\shared\supportpackages\visionzynq\bin\target\sdcard\visionzynq-zc706-hdmicam\visionzynq-refdes\visionzynq-zc706-hdmicam.dtb'
       DownloadDestination: '/mnt/visionzynq-customtgt'
    DownloadDtbDestination: '/mnt/visionzynq-customtgt'

## Copying DTB image located at /mnt/visionzynq-refdes/visionzynq-zc706-hdmicam.dtb to /mnt/devicetree.dtb
## Copying FPGA image located at /mnt/visionzynq-refdes/visionzynq-zc706-hdmicam.bit to /mnt/system.bit
## Rebooting board ...........
## Reboot complete

If you do not have this object defined in the workspace, create an object that contains a connection to the board.

vz = visionzynq

vz = 


visionzynq

   Device Information:
       DeviceName: 'ZedBoard FMC-HDMI-CAM'
    DeviceAddress: '192.168.4.2'
         Username: 'root'
         Password: 'root'
             Port: 22

Download a custom FPGA image file, such as one you created using the IP core generation workflow in the HDL Workflow Advisor, to the Zynq device. Specify the device tree file name that matches your board and the interface used by the FPGA user logic in your image. This example shows the device tree filename for a design that has an AXI4-Stream Video interface.

downloadImage(vz, ...
'FPGAImage','work\hdl_prj\vivado_ip_prj\mydesign_axi.bit', ...
'DTBImage','visionzynq-zedboard-hdmicam-axi-video.dtb');
### ConfiguringFPGA image ...
## Transferring image to hardware SD card:
              DownloadKind: 'FPGAImage'
              DownloadMode: 'interactive'
            DownloadSource: 'work/hdl_prj/vivado_ip_prj/mydesign_axi.bit'
                  DTBImage: 'toolbox/shared/supportpackages/visionzynq/bin/target/sdcard/visionzynq-zedboard-hdmicam/visionzynq-refdes/visionzynq-zedboard-hdmicam-axi-video.dtb'
       DownloadDestination: '/mnt/visionzynq-customtgt'
    DownloadDtbDestination: '/mnt/visionzynq-customtgt'

## Copying DTB image located at /mnt/visionzynq-refdes/visionzynq-zedboard-hdmicam-axi-video.dtb to /mnt/devicetree.dtb
## Copying FPGA image located at work/hdl_prj/vivado_ip_prj/mydesign_axi.bit to /mnt/system.bit
## Rebooting board ...........
## Reboot complete

Input Arguments

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Connection properties specified as a visionzynq object that connects from the host computer to the Zynq board.

FPGA image filename and relative or absolute folder location, specified as a character vector. This argument specifies the image to download to the SD card and load into the FPGA.

Example: 'work\hdl_prj\vivado_ip_prj\mydesign_axi.bit'

Device tree configuration filename, specified as a character vector. These files ship with the software, and the filenames indicate the board and the interface type. For example, use 'visionzynq-zcu102-hdmicam.dtb' with the Xilinx® Zynq UltraScale+™ MPSoC ZCU102 Evaluation Kit and with FPGA user logic that has the default Vision HDL Toolbox custom pixel-streaming interface. Use 'visionzynq-zcu102-hdmicam-axi-video.dtb' with the Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit and with FPGA user logic that has an AXI4-Stream Video interface.

If you omit this argument, the function loads a device tree for the Vision HDL Toolbox custom pixel-streaming interface. If your FPGA image uses the AXI4-Stream Video interface and you do not load the correct device tree, when you simulate your model with logic running on the board, you receive this error message. 

command "/mnt/visionzynq-tools/visionzynq-target-dev.elf --write --device=/dev/mwipcore_vht2vs --address=0x00 0x01".
    Error evaluating 'StartFcn' callback of SubSystem block (mask) 
'gm_vzImageRotation_PixelStream_tgthw_interface/Video Capture/VisionZynq Internal/FrameCapture_Init/Frame Format Check'. 
Callback string is 'visionzynq.internal.vzmask(gcb, 'FrameFormatCheckCb','StartFcn');' 
Caused by: Error executing command "/mnt/visionzynq-tools/visionzynq-target-dev.elf --write --device=/dev/mwipcore_vht2vs --address=0x00 0x01"

Version History

Introduced in R2016a

See Also

Functions