Receive Signal Waveform Using DDR4 on Xilinx RFSoC Device
This example shows how to design, simulate, and deploy a system to write and read the captured RF samples from external double data rate 4 (DDR4) memory in Simulink® with an SoC Blockset® implementation targeted on the Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit. In this example, you can write the captured samples of an analog-to-digital converter (ADC) into external programmable logic (PL) DDR4 memory, read the samples from the PL DDR4 memory, and send them to the processor to display. A tone signal is generated in FPGA using a numerically controlled oscillator (NCO) to verify the receive path.
Supported Hardware Platforms
Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit and XM500 balun card
Design Task and System Specifications
Consider an RF application that requires accessing external DDR4 memory to capture RF samples at a high data rate. In this example, the design task is to design a control algorithm that writes and reads captured RF samples from the external PL DDR4 memory. To verify RF samples captured on the DDR4, send a sinusoid tone from the FPGA to the digital-to-analog converter (DAC) of the RF Data Converter (RFDC) block (output of the DAC is looped back to the ADC input), and receive the data back on the FPGA. The following are the system specifications.
ADC and DAC sampling rate = 2048 MSPS
Number of ADC channels = 1
Number of DAC channels = 1
Digital data interface = Real
Design Using SoC Blockset
Create an SoC model
soc_ddr4datacapture_top as the top model and set the hardware board to
Xilinx Zynq Ultrascale+ RFSoC ZCU111 evaluation kit. This model includes the FPGA model
soc_ddr4datacapture_fpga and the processor model
soc_soc_ddr4datacapture_proc, which are instantiated as model references. The top model also includes the Memory Channel and Memory Controller blocks, which share the external memory between the FPGA and the processor.
RF Data Converter Configuration
An RFSoC device has its RF data converter connected to the programmable logic. To configure the ADC and DAC settings, use the RFDC block. The block provides an interface to the Xilinx RF Data Converter IP in Simulink for modeling a wireless system destined for implementation on Xilinx RFSoC device.
To meet the system requirement of 2048 MSPS as the data rate for DACs and ADCs, you must choose the values of the Interpolation mode, Decimation mode, and Samples per clock cycle parameters such that the effective clock cycle (sample rate) for the wireless algorithm FPGA is in the desirable range. The parameter values are displayed on the block under Stream clock frequency after you click Apply.
For this example, in the DAC tab, set Interpolation mode to 8 and Samples per clock cycle to
4. In the ADC tab, set Decimation mode to
8 and Samples per clock cycle to
4. These values imply a Stream clock frequency value of 2048/(8*4) = 64 MHz.
Hardware Logic Design
The FPGA model
soc_ddr4datacapture_fpga contains two subsystems,
DAC Tone Generation, which is connected to the DAC portion of the RFDC block, and
ADC Capture, which is connected to the ADC portion.
DAC Tone Generation subsystem, four consecutive samples of the sinusoid waveform are generated in parallel by using four HDL Optimized NCO blocks. Each HDL Optimized NCO block has a different offset. The four samples comprise 64 bits of data and have the same width as AXI-Stream data.
ADC Capture subsystem uses a trigger and the DDR4 capture logic to capture ADC RF samples and write them to the DDR4 memory frame by frame. After the write operation is complete, the subsystem reads and sends the data to the processor to display the captured signal. The register,
triggerFreq from the processor controls the trigger and capture logic.
Processor Logic Design
The processor logic contains an event-based task driven by the arrival of data from the FPGA through the DDR memory. The processor algorithm task is denoted as
dataTask in the Task Manager block and is specified as event driven. The Task Manager block schedules data asynchronously by means of the buffer ready event
rdEvent in the memory channel, denoting the arrival of a frame of data from the FPGA. The algorithm itself is modeled under the
Processor Algorithm Wrapper subsystem in the processor model
soc_ddr4datacapture_proc and connected to the Task Manager block at the top level. To operate on the data received as a frame of four packed samples with the
uint64 data type, you must first unpack and restore the signedness of the data. The output of the
Processor Algorithm Wrapper subsystem is then connected to the Spectrum and Time scope for visualization. In a separate
Initialize Function subsystem, various registers on the FPGA subsystems are initialized with their default values.
Run the model and visualize the sinusoid tone generated from the FPGA on the spectrum analyzer scope named DAC Output.
The waveform is looped back from the FPGA to the processor through the RFDC block, the
ADC Capture subsystem in FPGA, and the DDR4 memory block for capturing the waveform. In the processor system, the waveform is visualized in the frequency domain using a Spectrum scope block named ADC Captured Signal. The data is observed on the spectrum scope with a substantial delay after the start of the simulation. This delay is because of the delay in the availability of the first frame of data through the DDR4 to the scope, which is due to the length of the loopback data path.
Observe that both the transmitted and received signal show a tone of 5 MHz.
Implement and Run on Hardware
Connect the SMA connector on the XM500 balun card to complete the loopback between the DAC and ADC, according to these connections.
DAC229_T1_CH2(J5) to ADC224_T0_CH0(J4).
To implement the model on a supported SoC board, use the SoC Builder tool. Ensure that the Hardware Board is set to
Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit in the System on Chip tab of the Simulink toolstrip.
To open SoC Builder, click Configure, Build, & Deploy. After the SoC Builder tool opens, follow these steps.
Select Build Model on the Setup screen. Click Next.
Click Next on the Review Task Map screen.
Click View/Edit Memory Map on the Review Memory Map screen to view the memory map. Click Next.
Specify the project folder on the Select Project Folder screen. Click Next.
Select Build External mode on the Select Build Action screen. Click Next.
Click Validate on the Validate Model screen to check the compatibility of the model for implementation. Click Next.
Click Build on the Build Model screen to begin building the model. An external shell opens when FPGA synthesis begins. Click Next.
Click Test Connection on Connect Hardware screen to test the connectivity of the host computer with the SoC board. Click Next to go to the Run Application screen.
The FPGA synthesis can take more than 30 minutes to complete. To save time, you can use the provided pregenerated bitstream by following these steps.
Close the external shell to terminate the FPGA synthesis.
Copy the pregenerated bitstream to your project folder by entering this command at the MATLAB command prompt.
Click Load and Run button to load the pregenerated bitstream and run the model on the SoC board.
After the bit file is loaded, open the generated software model.
Run the model in external mode by clicking Monitor & Tune. You can control the configuration from the Simulink model. Copy the spectrum analyzer from the top model and connect to the rate transition block as shown in this figure, and run the model. You can observe the received signal waveform of 5 MHz in the spectrum analyzer.
This example shows how to design a system to write and read the captured RF samples from external DDR4 memory. You simulated and deployed the design on the Xilinx Zynq UltraScale+ ZCU111 evaluation kit using SoC Blockset. You can use this example as a reference for designing your application that requires DDR4 for data capture.