SoC Blockset™ enables simulation and evaluation of shared memory transactions in Simulink®. To include a memory system in your SoC model, configure a memory controller for the desired number of memory channels, and then connect the controller to memory channel blocks for arbitrating and handling memory traffic.
SoC Blockset enables the simulation and evaluation of shared memory transactions in Simulink. Visualize post-simulation performance and bandwidth metrics before deploying to SoC device by using the Logic Analyzer app.
|Memory Channel||Stream data through a memory channel (Since R2019a)|
|Memory Controller||Arbitrate memory transactions for one or more Memory Channel blocks (Since R2019a)|
|AXI4 Random Access Memory||Model random access through external memory (Since R2022b)|
|AXI4-Stream to Software||Stream AXI4 data from FPGA to software (Since R2022b)|
|Software to AXI4-Stream||Stream AXI4 data from software to FPGA (Since R2022b)|
|AXI4 Video Frame Buffer||Model connection between two hardware algorithms through external memory (Since R2022b)|
|Memory Traffic Generator||Generate traffic towards memory controller (Since R2019a)|
|Register Channel||Timing model for transfer of register values (Since R2019a)|
|Interrupt Channel||Send interrupt to processor from hardware (Since R2020b)|
|AXI4 Master Sink||Receive random access memory data (Since R2019a)|
|AXI4 Master Source||Generate random access memory data (Since R2019a)|
|Stream Data Sink||Receive continuous stream data (Since R2019a)|
|Stream Data Source||Generate continuous stream data (Since R2019a)|
Hardware Logic Connectivity
|SoC Bus Selector||Convert bus to control signals (Since R2019a)|
|SoC Bus Creator||Convert control signals to bus (Since R2019a)|
|Stream FIFO||Control backpressure between hardware logic and upstream data interface (Since R2019a)|
|Stream Connector||Connect two IPs with data streaming interfaces (Since R2019a)|
|IP Core Register Read||Model register writes from software to hardware (Since R2020a)|
Processor Software Connectivity
|Register Read||Read data from a register region on the specified IP core (Since R2019a)|
|Register Write||Write data to a register region on the specified IP core (Since R2019a)|
|Stream Read||Stream data from shared memory to processor algorithms (Since R2019a)|
|Stream Write||Stream data from processor algorithms to shared memory (Since R2020b)|
|Logic Analyzer||Visualize, measure, and analyze transitions and states over time|
|Memory Mapper||Configure memory map for SoC application (Since R2019a)|
- Memory and Register Data Transfers
Introduction to memory and register transfers.
- External Memory Channel Protocols
Supported memory channel protocols and control signals.
- AXI4-Stream Interface
How to design your model for AXI4-Stream vector or scalar interface generation.
- Simplified AXI4 Master Interface
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
- AXI4-Stream Video Interface
How to design your model for IP core generation with AXI4-stream video interfaces.
- Simulation Diagnostics
SoC Blockset enables simulation and evaluation of memory transactions in Simulink without the need to deploy a model to an SoC device.
- Simulation Performance Tips
Suggestions for enhancing simulation performance of SoC models.
- Simulation Performance Plots
SoC Blockset enables post-simulation analysis of memory diagnostic data.
- Memory Performance Information from FPGA Execution
Obtain memory interconnect traffic information from a design running on FPGA.