# Sinusoidal Measurement (PLL)

Estimate sinusoidal characteristics using a phase-locked loop

**Libraries:**

Simscape /
Electrical /
Control /
Measurements

## Description

The Sinusoidal Measurement (PLL) block estimates the frequency, phase angle, and magnitude of a single-phase sinusoidal signal or individual phases of a multiphase sinusoidal signal. The block uses an enhanced phase-locked loop (PLL) strategy to estimate these sinusoidal characteristics of the input signal.

Use this block in control applications when the frequency, phase angle, or magnitude is required and cannot be measured directly. To provide faster phase locking for balanced three-phase input signals, use the Three-Phase Sinusoidal Measurement (PLL) block.

### Equations

The phase-locked loop generates a sinusoid that approximates the input signal
*u(t)* with the form:

$$y(t)=A(t)\mathrm{sin}\left({\varphi}_{0}+{\displaystyle \int 2\pi f(t)dt}\right),$$

where:

*y*is the estimate of the input signal.*A*is the estimate of the amplitude of the input signal.*ϕ*is the initial phase angle of the input signal._{0}

The estimated phase angle *ϕ* is the angle of this
generated sinusoid:

$$\varphi (t)={\varphi}_{0}+{\displaystyle \int 2\pi f(t)dt},$$

where *f* if the frequency of the sinusoid, and
*ϕ _{0}* is the initial phase
angle.

This diagram shows the overall structure of the phase-locked loop.

In the diagram:

The phase detector produces an error signal relative to the phase difference

*e*between the input sinusoid_{ϕ}*u*and the synthesized sinusoid*y*. It also outputs an estimate of the amplitude*A*.The loop filter provides an estimate of the input angular frequency

*ω*by filtering out the high-frequency components of the phase difference. The block also outputs the converted frequency*f*in Hz.The voltage-controlled oscillator integrates the angular speed to produce the phase estimate

*ϕ*. The oscillator also generates the normalized synthesized sinusoid*(1/A)y*which it sends to the Phase Detector for comparison.

## Examples

## Assumptions and Limitations

The input signal, **u**, must not have a DC bias and must be in this form:

$$u(t)=A\cdot \mathrm{sin}\left(\omega (t)+\theta \right).$$

## Ports

### Input

### Output

## Parameters

## References

[1] Karimi-Ghartemani, M., and M. R. Iravani. "A New Phase-Locked Loop (PLL)
System." *IEEE Transactions on Industrial Electronics.* Proceedings
of the 44th IEEE Symposium on Circuits and Systems, vol. 1, pp. 421-424. IEEE,
2001..

## Extended Capabilities

## Version History

**Introduced in R2017b**