DVB-S2 LDPC Decoder

Decode LDPC code according to DVB-S2 standard

Since R2022a

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Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The DVB-S2 LDPC Decoder block implements a low-density parity-check (LDPC) decoder using layered belief propagation with min-sum approximation and normalized min-sum approximation algorithms for decoding LDPC codes according to the Digital Video Broadcast Satellite Second Generation (DVB-S2) standard. The block accepts log-likelihood ratio (LLR) values, a stream of control signals, a frame type, and a code rate as inputs and outputs decoded bits, a stream of control signals, and a signal that indicates when the block is ready to accept new inputs.

The DVB-S2 LDPC Decoder block supports early termination to help improve decoding performance and convergence speeds at high signal-to-noise-ratio (SNR) conditions. The block supports scalar values through the input/output (I/O) interface. It also supports forward error correction (FEC) frames of type normal and short with all the code rates supported by the DVB-S2 standard. For more information about the DVB-S2 standard, see [1].

The block provides an architecture suitable for HDL code generation and hardware deployment. You can use this block in DVB-S2 modem development.

Examples

DVB-S2 HDL LDPC Encoder

Implement DVB-S2 LDPC encoding using Simulink® blocks that are optimized for HDL code generation.

Open Script

Decode and Recover Message Using DVB-S2 Standard FEC Decoder

Decode and recover message from codeword using FEC decoder according to DVB-S2 standard.

Open Script

Ports

Input

data — LLR values

scalar

LLR values, specified as a scalar.

For HDL code generation, specify this value in signed fixed-point format. The input word length must be in the range from 4 to 16.

Data Types: int8 | int16 | signed fixed point

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the input frame

• end — Indicates the end of the input frame

• valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

frameType — Type of FEC frame

scalar

Type of FEC frame, specified as a Boolean scalar.

• 0 — Indicates a normal frame

• 1 — Indicates a short frame

Dependencies

To enable this port, set the FEC frame source parameter to Input port.

Data Types: Boolean

codeRateIdx — Code rate index

integer

Code rate index, specified as an integer. Code rate index values range from 0 to 10. Each code rate index value represents a specific code rate, as shown in this table.

codeRateIdx Value	Code Rate
0	1/4
1	1/3
2	2/5
3	1/2
4	3/5
5	2/3
6	3/4
7	4/5
8	5/6
9	8/9
10	9/10 (not supported for short frame)

You must specify this value in the fixdt(0,4,0) format.

Dependencies

To enable this port, do one of the following:

• Set the FEC frame source parameter to Input port.

• Set the FEC frame source parameter to Property and the Code rate source parameter to Input port.

Data Types: fixdt(0,4,0)

iter — Number of iterations

scalar

Number of iterations, specified as an unsigned integer in the range from 1 to 63.

If you specify an iter value greater than 63 or less than 1, the block overrides your specification and sets the iter value to 8 before decoding.

Dependencies

To enable this port, set the Decoding termination criteria parameter to Max or Early and the Source for number of iterations parameter to Input port.

Data Types: uint8

Output

data — Decoded bits

scalar

Decoded bits, returned as a Boolean scalar.

Data Types: Boolean

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the output frame

• end — Indicates the end of the output frame

• valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

nextFrame — Block ready indicator

scalar

Block ready indicator, returned as a Boolean scalar.

The block sets this signal to 1 (true) when the block is ready to accept the start of the next frame. If the block receives an input ctrl.start signal while nextFrame is 0 (false), the block discards the frame in progress and begins processing the new data.

Data Types: Boolean

parityCheck — Parity check status indicator

scalar

Parity check status indicator, returned as a Boolean scalar. The port indicates the status of the parity check after the decoding operation.

• 0 — Indicates that the parity check failed

• 1 — Indicates that the parity check passed

Dependencies

To enable this port, select the Enable parity check output port parameter.

Data Types: Boolean

actIter — Actual number of iterations

scalar

Actual number of iterations the block takes to decode the output, returned as a scalar.

Dependencies

To enable this port, set the Decoding termination criteria parameter to Early.

Data Types: uint8

Parameters

FEC frame source — Source for FEC frame

Input port (default) | Property

Select the FEC frame source as Input port or Property.

• Property — Select this option to enable the FEC frame type parameter.

• Input port — Select this option to enable the frameType port.

FEC frame type — FEC frame type

Normal (default) | Short

Select the FEC frame type as Normal or Short.

Dependencies

To enable this parameter, set the FEC frame source parameter to Property.

Code rate source — Source for code rate

Property (default) | Input port

Select the code rate source as Property or Input port.

• Property — Select this option to enable the Code rate parameter.

• Input port — Select this option to enable the codeRateIdx port.

Dependencies

To enable this parameter, set the FEC frame source parameter to Property.

Code rate — Code rate

1/4 (default) | 1/3 | 2/5 | 1/2 | 3/5 | 2/3 | 3/4 | 4/5 | 5/6 | 8/9 | 9/10

Select the code rate.

Note

Code rate of 9/10 is not supported for short frame.

Dependencies

To enable this parameter, set the FEC frame source parameter to Property and set the Code rate source parameter to Property.

Algorithm — LDPC decoding algorithm

Min-sum (default) | Normalized min-sum

Select the type of LDPC decoding algorithm. For more information, see Algorithm.

• Min-sum — Use this option to select the layered belief propagation algorithm with a min-sum approximation. For more information, see Min-Sum Approximation.

• Normalized min-sum — Use this option to select the layered belief propagation algorithm with a normalized min-sum approximation. For more information, see Normalized Min-Sum Approximation.

Scaling factor — Scaling factor for normalized min-sum decoding

0.75 (default) | scalar in the range 0.5 to 1, incremented by 0.0625

Specify the scaling factor as a scalar in the range 0.5 to 1, incremented by 0.0625.

Dependencies

To enable this parameter, set the Algorithm parameter to Normalized min-sum.

Decoding termination criteria — Termination criteria

Max (default) | Early

Select the decoding termination criteria.

• Max — Terminate decoding when the block reaches the number of iterations specified in the block mask or through the iter input port.

• Early — Terminate decoding when the block meets all of the parity checks or when the block reaches the maximum number of iterations provided in the block mask.

Source for number of iterations — Source selection for number of iterations

Property (default) | Input port

Select the source for specifying the number of iterations.

You can set the number of iterations by using either an input port or a parameter.

• Property — Select this option to enable the Number of iterations parameter.

• Input port — Select this option to enable the iter port.

Number of iterations — Number of decoding iterations

8 (default) | integer in the range from 1 to 63

Specify the number of decoding iterations.

Dependencies

To enable this parameter, set the Decoding termination criteria parameter to Max and the Source for number of iterations parameter to Property.

Maximum number of iterations — Maximum number of decoding iterations

8 (default) | integer in the range from 1 to 63

Specify the maximum number of decoding iterations.

Dependencies

To enable this parameter, set the Decoding termination criteria parameter to Early and set the Source for number of iterations parameter to Property.

Enable parity check output port — Parity check status

off (default) | on

Select this parameter to enable the parityCheck output port to view the status of the parity check.

Algorithms

This figure shows the architecture block diagram of the DVB-S2 LDPC Decoder block. The Controller block controls the layer and iteration count of the decoding process. The Variable node RAM block stores the variable node (VN) messages, and the Check node RAM block stores the check node (CN) messages. The Functional Unit block calculates the VN messages and CN messages based on layered belief propagation and either the normalized min-sum approximation algorithm or the min-sum approximation algorithm. The Termination/Parity check status block calculates the parity checks and provides the parity check status after each iteration. For more information about decoding algorithms, see the following sections.

Belief Propagation Decoding

The implementation of the belief propagation algorithm is based on the decoding algorithm presented in [2]. For a transmitted LDPC-encoded codeword, c, where $$c=(c_0,c_1,\mathrm{...},c_{n-1})$$, the input to the LDPC decoder is the log-likelihood ratio (LLR) value $$L(c_i)=\log \left(\frac{\mathrm{Pr}(c_i=0|\text{channel output for }{c}_i)}{\mathrm{Pr}(c_i=1|\text{channel output for }{c}_i)}\right)$$.

In each iteration, the key components of the algorithm are updated based on these equations:

$$L(r_{ji})=2\text{atanh}\left({\displaystyle \prod _{i^{\prime }\in V_j\backslash i}\tanh \left(\frac{1}{2}L(q_{i^{\prime }j})\right)}\right)$$,

$$L(q_{ij})=L(c_i)+{\displaystyle \sum _{j^{\prime }\in C_i\backslash j}L(r_{j^{\prime }i})}$$, initialized as $$L(q_{ij})=L(c_i)$$ before the first iteration, and

$$L(Q_i)=L(c_i)+{\displaystyle \sum _{j^{\prime }\in C_i}L(r_{j^{\prime }i})}$$.

At the end of each iteration, $$L(Q_i)$$ is an updated estimate of the LLR value for the transmitted bit $$c_i$$. The value $$L(Q_i)$$ is the soft-decision output for $$c_i$$. If $$L(Q_i)<0$$, the hard-decision output for $$c_i$$ is 1. Otherwise, the output is 0.

Layered Belief Propagation Decoding

The implementation of the layered belief propagation algorithm is based on the decoding algorithm presented in [3], Section II.A. The decoding loop iterates over subsets of rows (layers) of the PCM. For each row, m, in a layer and each bit index, j, the implementation updates the key components of the algorithm based on these equations:

(1) $$L(q_{mj})=L(q_j)-R_{mj}$$,

(2) $$A_{mj}={\displaystyle \sum _{\begin{array}{c}n \in N\left(m\right)\\ n\ne j\end{array}}\text{ψ}(L(q_{mn}))}$$,

(3) $$s_{mj}={\displaystyle \prod _{\begin{array}{c}n \in N\left(m\right)\\ n\ne j\end{array}}\text{sign}(L(q_{mn}))}$$,

(4) $$R_{mj}=-s_{mj}\text{ψ}(A_{mj})$$, and

(5) $$L(q_j)=L(q_{mj})+R_{mj}$$.

For each layer, the decoding equation (5) works on the combined input obtained from the current LLR inputs $$L(q_{mj})$$ and the previous layer updates $$R_{mj}$$.

Because only a subset of the nodes is updated in a layer, the layered belief propagation algorithm is faster compared to the belief propagation algorithm. To achieve the same error rate as attained with belief propagation decoding, use half the number of decoding iterations when using the layered belief propagation algorithm.

Min-Sum Approximation

The implementation of the min-sum approximation algorithm follows the layered belief propagation algorithm with equation (2) replaced by

$$A_{mj}=\underset{\begin{array}{c}n \in N\left(m\right)\\ n\ne j\end{array}}{\min }(\left|L(q_{mn}) \right|\cdot \alpha )$$,

where α is 1.

Normalized Min-Sum Approximation

The implementation of the normalized min-sum approximation algorithm follows the layered belief propagation algorithm with equation (2) replaced by

$$A_{mj}=\underset{\begin{array}{c}n \in N\left(m\right)\\ n\ne j\end{array}}{\min }(\left|L(q_{mn}) \right|\cdot \alpha )$$,

where α is in the range [0, 1] and is the scaling factor specified by the Scaling factor parameter. This equation is an adaptation of equation (4) presented in [4].

Latency

The latency of the block varies based on the frame type, code rate, and number of iterations.

The latency of the block is equal to (r x t) + d + inputLen. In this calculation, r is the number of iterations, t is the number of clocks required to decode one iteration, d is the pipeline delays, which are a fixed value equal to 9, and inputLen is the length of the input data.

The table shows the number of clocks the block requires to decode one iteration for normal and short frame types with different code rates.

Code Rate	Number of Clocks Per Iteration
	Normal	Short
1/4	20,520	5328
1/3	20,160	5040
2/5	19,872	4968
1/2	18,000	4360
3/5	19,008	4752
2/3	14,880	3720
3/4	14,040	3168
4/5	13,536	2880
5/6	13,200	2896
8/9	10,400	2600
9/10	10,244	Code rate not supported for short frame

This figure shows a sample output and latency of the DVB-S2 LDPC Decoder block for the default configuration when you specify frameType as 0 (Normal frame) and codeRateIdx as 5 (2/3 code rate). The latency of the block is 183,849 clock cycles.

EbNo and BER Plots

This section shows the EbNo and BER plots of the block for specified inputs and parameter settings.

This plot shows the performance of the block for a 4 bit QPSK modulated LLR input of short and normal frames with code rates 1/2 and 3/4, respectively, when you set the Algorithm parameter to Min-sum.

This plot shows the performance of the block for a 4 bit 16-APSK modulated LLR input of short and normal frames with code rates 3/5 and 5/6, respectively, when you set the Algorithm parameter to Min-sum.

Performance

The performance of the synthesized HDL code varies with the target and synthesis options. It also varies based on the type of algorithm, frame type source, code rate source, decoding termination criteria, and word length of the input LLR values.

This table shows the resource and performance data synthesis results of the block for the supported DVB-S2 standard when you specify the input LLR values in fixdt(1,4,0) format and set the Algorithm parameter to Min-sum, the Number of iterations parameter to 8, and the FEC frame source parameter to Input port. The generated HDL is targeted to the Xilinx^® Zynq^®Ultrascale+™ MPSoC - ZCU102 Evaluation Board.

Slice LUTs	Slice Registers	Block RAMs	Maximum Frequency in MHz
14,390	8,712	135	319.30

References

[1] ETSI Standard EN 302 307 V1.4.1: Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2), European Telecommunications Standards Institute, Valbonne, France, 2005-03.

[2] Gallager, R. “Low-Density Parity-Check Codes.” IEEE Transactions on Information Theory 8, no. 1 (January 1962): 21–28. https://doi.org/10.1109/TIT.1962.1057683.

[3] Hocevar, D.E. “A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes.” In IEEE Workshop On Signal Processing Systems, 2004. SIPS 2004, 107–12. Austin, Texas, USA: IEEE, 2004. https://doi.org/10.1109/SIPS.2004.1363033.

[4] Chen, Jinghu, R.M. Tanner, C. Jones, and Yan Li. "Improved Min-Sum Decoding Algorithms for Irregular LDPC Codes." In Proceedings. International Symposium on Information Theory, 2005. ISIT 2005. https://doi: 10.1109/ISIT.2005.1523374.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Version History

Introduced in R2022a