Can a Verilog RTL be simulated using Matlab Testbench?

Is there any possibility to co-simulate the verilog RTL and a matlab testbench. If it is possible is there any restrictions for using it and please let me know how to invoke the simulation.

Answer 1

[Bharath Venkataraman]

You can cosimulate Verilog code with MATLAB or Simulink. There are examples provided in the HDL Verifier product for this workflow.

Here are two examples on that page that may be useful: http://www.mathworks.com/help/hdlverifier/examples/cosimulation-wizard-for-matlab-system-object.html http://www.mathworks.com/help/hdlverifier/examples/verify-viterbi-decoder-using-matlab-system-object-and-mentor-graphics-modelsim.html