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Bharath Venkataraman

Last seen: Today Active since 2013

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Answered
signal over lapping in Down sampler output for ZYNQ FPGA
Are you trying to implement a chaneelizer? If so, here is the behavioral version in DSP System Toolbox and its HDL equivalent.

19 giorni ago | 0

Answered
difference in column based and element based decimated output of a down sampler
Muhammad, I assume that you are doing this as a multirate system in the FPGA. To mimic that behavior, send in scalar input to th...

19 giorni ago | 0

Answered
Difference in the output of CIC decimator while using with unbuffer and without unbuffer
Could you please provide a model that shows this behavior (you may want to try it using a fixed known input first)? Are you sen...

23 giorni ago | 0

Answered
How do I generate HDL Code for my model that has frame based communication in Simulink HDL Coder 2.1 (R2011a)?
I have one clarification on your question. When you say "frame based communication" - are you referring to processing multiple s...

27 giorni ago | 0

Answered
Different CIC decimator Response in normal simulation and FPGA implementation
It would be helpful to see your model - are you using the CIC Decimation block? Did you build your own? Have you tired using the...

27 giorni ago | 0

Answered
Vision HDL Toolbox Support - available inputs
Currently, the only way to do it live with the Vision HDL Toolbox Support Package for Xilinx Zynq is with the FMC + HDMI camera....

28 giorni ago | 0

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Answered
Error message "Found unsupported dimensions on matrix type at input port: 0" has occurred while generating HDL(Verilog) Code from matlab algorithm.
It would be helpful to see the code (at least at the high level of the testbench and top level design). For conversion to HDL, y...

circa un mese ago | 0

Answered
Xilinx System Generator error with storage container type
Hi George, Xilinx System Generator is not a MathWorks product. I recommend reaching out directly to Xilinx for troubleshooting ...

circa un mese ago | 0

Answered
Vision HDL Toolbox Support - available inputs
You can capture the video onto your computer and use the Vision HDL Toolbox model with a video source. This is shown in this Vi...

circa un mese ago | 0

Answered
How to generate verilog code for thisbelow function using HDL coder?
You can use the real divide hdl optimized block. Other options include the reciprocal block followed by a multiply or the divide...

circa un mese ago | 0

Answered
Unable to run HDL QPSK Transmitter and Receive
You need DSP HDL Toolbox to run this example. Please reach out to support to see why you do not have access to this product.

circa 2 mesi ago | 0

Answered
AD936x Receiver Transmitter blocks missing in Simulink library
Running the command "which zynqRadioQPSKRxAD9361AD9364SL" should show you where the Simulink model lives in your installation. T...

circa 2 mesi ago | 0

Answered
Code Generation for d flipflop
Do you really need to model the D Flip Flop (especially the clock)? If not, I suggest using the Delay block (with enable if you ...

2 mesi ago | 0

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Answered
Error evaluating 'InitFcn' callback of block_diagram 'hdlcoder_lteofdm_modDetect'. Callback string is 'simParams = hdlcoder_lteofdm_modDetectref_init; simParams = hdlcoder_lteofdm_modDetecthdl_init(simParams);
As John mentioned in the comments, the function mentioned in the Diagnosic Viewer, lteTestModel, is a function in the LTE Toolbo...

3 mesi ago | 0

Answered
Enable Not Working on Synchronous Subsystem
The synchronous state control behaves exactly like the HDL would, doing a divide by zero because the reciprocal block is a combi...

3 mesi ago | 0

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Answered
Test bench can't work for some 'entity' are not compiled in library 'xil_defaultlib'.
System Generator is a third-party blockset provided by Xilinx. For any further questions, please contact Xilinx technical suppor...

4 mesi ago | 0

Answered
Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version?
HDL Coder generates HDL code compliant with Verilog-2001. https://www.mathworks.com/help/hdlcoder/gs/language-and-tool-version-...

4 mesi ago | 1

Answered
How to get fractional delay filter in vhdl using matlab 2021a.
You can look at this example that shows how to quantize the filter before generating HDL.

4 mesi ago | 0

Answered
Why is my FFT HDL Optimized block running slower in FIL than Simulink?
This slowdown is due to the time it takes to send the data over from Simulink to the FPGA and back. You can use an Ethernet cab...

4 mesi ago | 0

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Answered
using bandpass filter on waveform
You can use the fdesign.bandpass function to design the filter. The resulting FIR or Biquad Filter can be used to generate HDL c...

5 mesi ago | 1

Answered
i m trying using converting signal processing block into hdl code , but some of the blocks are not compatible into hdl conversion .does anyone knows how to do it
Please check the Code Generation examples in Phased Array System Toolbox. The HDL code generation examples show how to implement...

6 mesi ago | 0

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Answered
Changing HDL FIR filter numerator while simulation is running
You can set the property Coefficients Source to input port and feed the coefficients via the input port. This will allow you to ...

6 mesi ago | 0

Answered
IIR Filter Coefficant Value
Click on File -> Export. There is an option to export the coefficients to the workspace (SOS, G will be exported as variables ac...

6 mesi ago | 0

Answered
Is matlab R2020a compatible with the latest xilinx system generator 2019.1?
I believe the answer is no. The question has been answered in this post.

7 mesi ago | 0

Answered
Hi, I am using R2014b but cant find the HDL code in Code menu, only C/C++ code. what should i do to genarate a HDLcode for my simulink model.
You likely do not have HDL Coder installed. Type ver at the MATLAB command prompt to see if you have HDL Coder installed.

7 mesi ago | 1

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Answered
Do Enabled Subsystems use multiplexers in generated HDL code?
In order to get different rates, either through clock enables or through multiple clocks, you need to model the signals at diffe...

7 mesi ago | 0

Answered
'/Serializer1D/HDL1DSe' error occurred when invoking 'getOutputSizeImpl' method of 'hdl.serializer1D'
I was able to avoid the error by setting the dimension of inputA to 1. Model attached.

7 mesi ago | 0

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Answered
How can I get the input names of the first level only in my simulink model?
You can use the SearchDepth parameter to specify the depth of the search. sysIns = find_system(bdroot,'SearchDepth',1, 'BlockT...

7 mesi ago | 0

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Answered
Warning: the font "Times" is not available, so "Lucida Bright" has been substituted, but may have unexpected appearance or behavor. Re-enable the "Times" font to remove this
What operation are you trying to eprform? Are you trying to generate HDL Code? If yes, do you have HDL Coder installed and lice...

8 mesi ago | 0

Answered
I am trying to run the Xilinx Demo in simulating but I get "Error in 'sysgenSSRIFFT/I.IM': Initialization commands cannot be evaluated."
"System Generator for DSP" is a third-party blockset provided by Xilinx. For questions related to System Generator, please conta...

8 mesi ago | 0

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