HDL Coder: Clock-rate pipelining example
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I would like to evaluate clock-rate pipelining functionality of HDL Coder. Is there any example available ?
Thanks in advance
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Girish Venkataramani
il 24 Giu 2015
Hello,
Yes, we are in the process of publishing an example for the clock-rate pipelining feature in R2015b. I'm happy to share this with you if you'd like. Can you share a little bit more on what your use-case is and what you are trying to achieve? I may be able to give you some guidance. This is a complex feature and requires some care in using it in such a way that it gives you the results you are expecting.
Girish
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Girish Venkataramani
il 25 Giu 2015
Hello Thibault
Yes, this kind of controller use-case is ideal for using clock-rate pipelining. Yes, I can certainly help you with that. Can you share a little more about your project/company etc? If you can, do you mind sharing your Simulink model - I could help you re-model it so that you can meet your latency requirements. Please let me know.
I will have the shipping example ready to share maybe within a week (or 2 at most).
Girish
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