HDL Coder: Clock-rate pipelining example

I would like to evaluate clock-rate pipelining functionality of HDL Coder. Is there any example available ?

Thanks in advance

Answer 1

[Girish Venkataramani]

Hello,

Yes, we are in the process of publishing an example for the clock-rate pipelining feature in R2015b. I'm happy to share this with you if you'd like. Can you share a little bit more on what your use-case is and what you are trying to achieve? I may be able to give you some guidance. This is a complex feature and requires some care in using it in such a way that it gives you the results you are expecting.

Girish

Answer 2

[Thibault Gadeyne]

Hello Girish,

I basically want to realize transfer functions or controllers running at limited speeds and I would be interested in using clock-rate pipelining to avoid slow delays. The final objective is to implement in a FPGA a plant model of a PMSM motor and a FOC controller. I tried to use the clock-rate pipelining option with a hand-made 1st order transfer function. The data sample time was 1e-6 and I set fundamental sample time to 1e-8. On the generated equivalent model the added pipeline delays run at 1e-6 sample time and not 1e-8 as I would like. The generated VHDL code doesn't seem to correspond to a clock-rate pipelining neither.

It would really help me if you can share with me the clock-rate pipelining example.

Thank you for your answer

Thibault

Answer 3

[Girish Venkataramani]

Hello Thibault

Yes, this kind of controller use-case is ideal for using clock-rate pipelining. Yes, I can certainly help you with that. Can you share a little more about your project/company etc? If you can, do you mind sharing your Simulink model - I could help you re-model it so that you can meet your latency requirements. Please let me know.

I will have the shipping example ready to share maybe within a week (or 2 at most).

Girish

[Thibault Gadeyne]

Hi Girish,

Thank you for your proposition. The design is still under construction. I'll let you know as soon as I have a first design validated.

Thibault