HDL Fifo outputs delayed signals

Hello,

My setup is the following: I fill up an HDL FIFO until it is full. From then on, it is used as a circular buffer (pushing and poping one value on every cycle).

The issue arose when connecting the output "Full" to input "Pop".

Without a delay in the feedback loop, the block generates no algebraic loop (seems unexpected to me). With a delay in the feedback loop, the block starts poping values one cycle too late: the FIFO was full one cycle earlier but did not generate the signal "Full" properly. This, in turn, triggers the assertion "Push on Fifo Full".

My understanding is that the delay block "sampleOutNum" takes as an input Num(t+1) and outputs Num(t). The HDL FIFO block output should be Num(t+1) and not Num(t). Similarly, block outputs Full and Empty should be generated by comparing Num(t+1) (not Num(t)) with Fifo_full and 0.

Any help is appreciated,

Answer 1

[Ludo Visser]

In my experience, the HDL FIFO block is broken in many ways.

As I understand its working, when you assert the pop input, the value is actually popped on the next cycle. I think this applies to all outputs: they are always one cycle "too late", so you need to model accordingly. However, as a side-effect, you can just loop the empty and full signals back to the inputs (push or pop) without a delay, as you observed.

If you force a modelling error, you can actually look under the mask of the HDL FIFO block and see how it's implemented. It's not pretty though.

[Sylvain R.]

Yes, you're right, the HDL Fifo, as I described it worked (no delay in the feedback loop). I understood my mistake after a few weeks.

I was looking to get the HDL Fifo behavior for simulation without the purpose of generating HDL Code. This approach was flawed, the HDL Coder block is meant to create functionnal code (and requires for that a delay on the outputs).

I ended up creating a new HDL Fifo block, with a simulation behavior suitable to our needs (the generated content itself being handled with a blackbox).