Generating a loop in VHDL using Simulink HDL Coder

How to write in Simulink HDL Coder to get for generate loop in VHDL?

Answer 1

[Tim McBrayer]

While there are certain constructs in Simulink where Simulink HDL Coder will generate a for-generate loop in VHDL, it is best not to be overly concerned about the style of code generation. There is no recipe for creating a for-generate loop.

Answer 2

[Andrew]

"There is a "For Iterator Subsystem" block to do for-loop in Simulink. But your task doesn't sound like it. You might want to consider the "Repeating Sequence" block from Simulink>Source library." [ loop-in-simulink ]

I don't think this solution will work for VHDL, but I may try it soon. Will this feature be added in newer simulink/HDL coder releases? I need to instantiate a block 127 times so I am also interested in this kind of feature.

[Tim McBrayer]

Neither of the mentioned Simulink constructs are currently supported by HDL Coder. They may exist in the testbench portion of the design, but cannot have HDL Code generated for them.