Does the IP Core Generation workflow in HDL Coder support asynchronous clock domains?

I am using the IP Core Generation workflow in HDL Coder. Since I am using an AXI-Lite interface, I have two clock domains in my generated code: IPCORE_CLK and AXI4_LITE_ACLK. I don't see a timing constraints file (.XDC) in the generated code, but I expect one because clock domain crossing will need to be managed. How is timing managed between the IPCORE_CLK and AXI4_LITE_ACLK clock domains? Are they asynchronous?

Answer 1

[MathWorks Support Team]

IP Core Generation does not support using different clocks for the IP core and the AXI interface. The IPCore_Clk and AXILite_ACLK must be synchronous and connected to the same clock source. The IPCore_RESETN and AXILite_ARESETN must be connected to the same reset source. This requirement is listed in the following documentation (second bullet point): https://www.mathworks.com/help/hdlcoder/ug/custom-ip-core-generation.html#mw_42c9f774-1f11-460f-a443-92d3d2061cca

The following documentation provides more information on synchronization of the IPCORE_CLK and AXI4_Lite_ACLK clock domain: https://www.mathworks.com/help/hdlcoder/ug/ip-core-reset-interface.html