luckfy zhang

Attivo dal 2018

Followers: 0 Following: 0

Statistica

Visualizza badge

Feeds

Domanda

How can I figure out how many delay units do I need in one part of Simulink HDL design?
Hi, Recently, I am interested in debuging your ZYNQ hwswcodesign model. The figure below is one part of Rx Data decoding bl...

oltre 5 anni fa | 1 risposta | 0

1

risposta

Domanda

How can I migrate MathWorks support on ZedBoard to Xilinx ZC702 board?
Hello, everyone: I have noticed MathWorks support on ZYNQ and AD9361 series algorithm development. All these tutorials are ...

quasi 6 anni fa | 1 risposta | 0

1

risposta

Domanda

Where can I set output and input port of an HDL-supported Simulink model?
I am using a Simulink model commqpsktxhdl. I have managed to output HDL code and I found that there 3 inputs including clk, clk-...

oltre 6 anni fa | 1 risposta | 0

1

risposta

Domanda

In simulink, Why does output datatype does not match to my settings?
Hello, everyone. I am using Xilinx System generator in the environment of Simulink. As you can see, I want to use a parallel...

oltre 6 anni fa | 0 risposte | 0

0

risposte