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simulation error using simple porm RAM while running the program
For this model to work, both RAMs should have the same input and output data types. It appears that the input and output of t...

circa 10 anni fa | 0

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errors in MATLAB/simulink while using logic analyzer
Currently, the Logic Analyzer System object can only show signals of a single rate. If the signals you are logging are different...

circa 10 anni fa | 1

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Displaying image in Simulink using pixel stream
Using the video viewer block instead of the matrix viewer will enable you to display the image. You likely need to set a sample ...

circa 10 anni fa | 0

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How to use FPGA multiplier efficiently?
Open the model, hit Ctrl-E and the Configuration Parameters dialog should open. Click into the HDL Code Generation section and g...

circa 10 anni fa | 0

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HDL IFFT optimize latency
The latency indicates the real-life behavior of the system on an FPGA or ASIC. To look at the data only when it is valid, use th...

circa 10 anni fa | 0

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The IIR filter in verilog created by filterbuilder cannot work!
Are you able to see whether the filter input has Xs when you look at it in the ModelSim wave viewer? You can also analyze the ot...

circa 10 anni fa | 0

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How to use FPGA multiplier efficiently?
Can you see what kind of reset you used for the HDL code? You likely want to set the register to have synchronous reset - this c...

circa 10 anni fa | 1

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Simulink 'Frame to Pixels' block error: computed fixed step size smaller than all the discrete sample times
Robert, You can resolve this issue by switching to the variable step solver with discrete states. Bharath

circa 10 anni fa | 0

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Real IFFT HDL Optimized
If you pass in doubles to the block, you will get doubles out.

circa 10 anni fa | 0

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Simulink HDL Coder - Filter - Fully Serial Interfacing
There is no timing diagram readily available, but if you look at the HDL code, you will see the interface is to provide a clock ...

oltre 10 anni fa | 0

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How to connect the Pixel Control Bus with camera driving procedure (ov7670)in quartus II(altera)
It does appear that you have to write an adapter to match the Pixel Control bus. More information (including a timing diagram) o...

oltre 10 anni fa | 0

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HDL code geneartaion for DPWM (digital pulse-width modulation)
The delay block, switch (including multi-port switch) and HDL Counter (as well as counter) blocks can be used for HDL code gener...

oltre 10 anni fa | 0

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Found unsupported division expression for HDL code generation; Signed input data type is not supported for division with Floor RoundMode.
The cos function is not supported for HDL code generation. You can use a lookup table (predefined array)that stores the cos valu...

oltre 10 anni fa | 1

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is there any program for writing matlab testbench according to its matlab code?
You can look at the <http://www.mathworks.com/examples/matlab-hdl-coder examples> provided with HDL Coder to see how a design an...

oltre 10 anni fa | 0

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HDL code generation of simple Discrete Transfer Function Block
When you change the data to fixed-point, each of the settings on the Discrete Transfer Function block needs to be specified. I s...

oltre 10 anni fa | 1

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HDL code generation of simple Discrete Transfer Function Block
Is it possible to attach your model? With floating point inputs, the Inherit via Internal Rule setting is required, but it appea...

oltre 10 anni fa | 1

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How to change the directory to run a hdl simulator?
You can launch Incisive from the MALTAB command line using the command *nclaunch* . nclaunch has a property setting for hdlsimdi...

oltre 10 anni fa | 0

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HDL conversion from Simulink
Filter Design HDL Coder generates HDL code for filters. HDL Coder allows you to generate for a larger set of functionality inclu...

oltre 10 anni fa | 0

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HDL coder buffer design in Simulink
You can use the HDL FIFO block. If that does not meet your needs, there are RAM and counter blocks available in Simulink. You ca...

oltre 10 anni fa | 0

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Debugging Errors for HDL Code Generation of IFFT
HDL code generation is not supported for the pulse generator and double to fixed-point blocks. Did you mean to generate HDL code...

oltre 10 anni fa | 0

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we are getting below error, when i am trying to generate verilog code from HDLIFFT model. Please help to understand/resolve this error.
For HDL code generation, the HDL IFFT block requires the input to be fed in one sample at a time. Please serialize the data and ...

oltre 10 anni fa | 0

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how can I konw the subset that hdl coder supported to transform a matlab to the verilog
If you have access to the Vision HDL Toolbox, there are a number of MATLAB System objects which can be used in image processing....

quasi 11 anni fa | 0

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How can I add a finish signal for HDL generation?
If you are referring to the latency of the system due to registers in the path between input and output, a valid flag is typical...

quasi 11 anni fa | 0

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Image Processing .m Code to HDL CODE
Is this an error or is it taking a long time? For the latter issue, reduce the amount of time you are running the simulation an...

quasi 11 anni fa | 0

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matlab code supporting HDL Code generator
If you are using Simulink, you can look at all the supported blocks by typing hdllib. You will find the modulator/demodulator an...

quasi 11 anni fa | 0

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how to add logic analyzer into Simulink ?
Do you have the dataset named templogic_logsout in the model? This option is in Simulink -> Configuration Parameters -> Data Im...

quasi 11 anni fa | 0

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Unable To Gererate VHDL Test Bench
Are you using Filter Design HDL Coder for the HDL Code? Or HDL Coder? please first try reducing the testbench data and that sho...

circa 11 anni fa | 0

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Why cant I get the same results IFFT block and HDL Optimized IFFT block.
The HDL Optimized FFT and IFFT don’t support natural order output in R2014a. The output of the HDL Optimized IFFT in your model ...

oltre 11 anni fa | 0

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question about HDL Coder
I assume that you are talking about the generation of the testbench itself? In Simulink, there is an option under Configurati...

oltre 11 anni fa | 0

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I am trying to design a IIR filter using fda tool and converted into verilog program but it is not synthesizable, how to make synthesizable verilog code for IIR filter.
What you want to do is design an IIR SOS filter and then you can use the Generate HDL option from fdatool.

oltre 11 anni fa | 0