How can I add a finish signal for HDL generation?

I created a algrithm using simulink and used HDL Coder to have my VHDL code generated. But I found that there's no flag indicate that the ouput result is already at the output port, I wonder if there's any way to solve this question? Any help would be appreciated. Thanks.

Answer 1

[Bharath Venkataraman]

If you are referring to the latency of the system due to registers in the path between input and output, a valid flag is typically modeled as an output of the design to indicate that data is ready.

This valid flag in the Simulink simulation should go high when the data is ready on the output. Once you verify this working in your Simulink design, you can generate HDL code for it and you will find the same valid output available in HDL as well.

[King]

Excuse me, but may I ask which block in simulink shall be used to implement such "valid flag" feature? Thank you for your support!

[Bharath Venkataraman]

That will depend on your design. You can use counters, delays, logical comparison operators to figure out when the valid flag output should go high.