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How to solve Algebric loop error without adding delay.
HDL Coder supports various memory interfaces including AXI4 and DDR memory access. https://www.mathworks.com/help/hdlcoder/ug/p...

oltre 3 anni fa | 0

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How to use signed bitconcat and bitsliceget?
The bitwise operator functions such as bitsliceget and bitconcat operate on underlying stored integer bits. Once bitwise operat...

oltre 3 anni fa | 0

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Problem in generating reusable Verilog code using Simulink HDL Coder
Feel free to reach out to technical support for this question. You may want to try to use the new subsystem reuse algorithm ava...

oltre 3 anni fa | 0

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Fast compilation Simulink Model : Recommeded Configuration of PC
It would be best to reach out to MathWorks support on this question.

oltre 3 anni fa | 0

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Usage of HDL and HLS blocks in same SystemGenerator for DSP design
can you share your model? Are you looking for a solution similar to this? https://www.mathworks.com/help/hdlcoder/ug/using-xil...

oltre 3 anni fa | 0

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How to serialize an HDL Coder function with a vector input ?
Can you share you algorithm? You would need to share a design.m and a testbech.m files. Thanks

oltre 3 anni fa | 0

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fixed point taylor sine/cosine approximation model
HDL Coder supports code generation for single precision trigonometric functions. Getting Started with HDL Coder Native Floatin...

oltre 3 anni fa | 0

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Which versions of Xilinx Vivado are supported with which release of HDL Workflow Advisor?
https://www.mathworks.com/help/hdlcoder/supported-hardware.html The supported official versions of Simulation and Synthesis too...

oltre 3 anni fa | 0

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Bitstream generation problem in HDL coder
Is it possible to attach a sample model? Feel free to reach out to MathWorks technical support on this question.

oltre 3 anni fa | 0

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up sample Simulink doesn't implement rate convertion on hdl coder
Please share your model. I do not see any such errors with a basic model with your sample settings.

oltre 3 anni fa | 0

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Can HDL coder produce code for unit delay with initial condition input
This feature is not currently supported and is on the future HDL Coder roadmap. For the block 'model/DUTSubsystem/Delay' ...

oltre 3 anni fa | 0

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PMSM is programed in FPGA using HDL coder.
In the motor control demo project the current control algorithm and speed control runs on FPGA and processor respectively and th...

oltre 3 anni fa | 0

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PMSM is programed in FPGA using HDL coder.
I think you are referring to this example. https://www.mathworks.com/videos/deploy-motor-control-algorithms-to-fpga-hardware-pro...

oltre 3 anni fa | 0

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Modeling S-R Flip flip for HDL code generation
Attached in an example model that works in 22a release.

oltre 3 anni fa | 0

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The top design unit selected for HDL code generation may not be inside a triggered subsystem.
The DUT targeted for code generation can be a whole model with root ports, or a regular virtual or atomic subystem, model refere...

oltre 3 anni fa | 0

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makehdltb. Dont open generated model.
I am assuming the act of simulation of your model opens scopes; HDL Coder simulates the model to collect stimulus and response o...

oltre 3 anni fa | 0

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What does 'coder.internal.indexShapeCheck>>errORWarnIF .... code generation assumption about size violated' mean?
This error is unexpected. Please share a sample project file that reproduces the error or reach out to technical support. HDL Co...

oltre 3 anni fa | 0

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How set block parameter over Zynq AXIS Lite bus?
https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-parameters.html Generate DUT Ports for Tunable Paramet...

oltre 3 anni fa | 1

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Zynq workflow error in step 4.2
This is an unepxected error issue. Please contact tech support for a solution and the next steps.

quasi 4 anni fa | 0

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how to solve this error?
Results from FPGA synthesis tool cannot be backannotated to model if they fall within Stateflow Block. This is a known limitatio...

quasi 4 anni fa | 0

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How to get list of all optimizations requested by subsystems in HDL Coder model?
>> hdlsaveparams('<path_to_the_dut>') >> help hdlsaveparams % PARAMETERSET = hdlsaveparams(DUT, FILENAME, FORCE_OVERWRITE)...

quasi 4 anni fa | 0

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Assertion failed: B:\matlab\src\cgir_hdl\pir_transforms\PrepareForFunctionCallPartition.cpp:3092:dataType == t
This is an unexpected error. Can you reach out MathWorks support team with the reproduction steps for a resolution and a worka...

quasi 4 anni fa | 1

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HDL coder error (Invalid feature 'ModelAdvisorGenerateNewStyleViewSwitchInGUI)
We are unable to reproduce this issue. Please contact local technical support for additional guidance.

quasi 4 anni fa | 0

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Workflow advisor synthesis error
Can you attach a sample project and design files to reproduce this error?

quasi 4 anni fa | 0

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Graph convolution neural network GCN in RTL
Deep Learning HDL Toolbox Prototype and deploy deep learning networks on FPGAs and SoCs https://www.mathworks.com/products/d...

quasi 4 anni fa | 0

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Do we have a standard procedure to convert SIMULINK model to HDL code?
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-...

quasi 4 anni fa | 0

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[Matlab Coder] Generate C code with hierarchy
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

quasi 4 anni fa | 0

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Break-up of CLAHE algorithm such that HDL Coder can support it.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

quasi 4 anni fa | 0

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Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

quasi 4 anni fa | 0

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generation matlab to VHDL
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

quasi 4 anni fa | 0