Risposto
Graph convolution neural network GCN in RTL
Deep Learning HDL Toolbox Prototype and deploy deep learning networks on FPGAs and SoCs https://www.mathworks.com/products/d...

oltre 4 anni fa | 0

Risposto
Do we have a standard procedure to convert SIMULINK model to HDL code?
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-...

oltre 4 anni fa | 0

Risposto
[Matlab Coder] Generate C code with hierarchy
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

oltre 4 anni fa | 0

Risposto
Break-up of CLAHE algorithm such that HDL Coder can support it.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

oltre 4 anni fa | 0

Risposto
Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

oltre 4 anni fa | 0

Risposto
generation matlab to VHDL
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

oltre 4 anni fa | 0

Risposto
How to use Matlab generated c code for vivado HLS ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

oltre 4 anni fa | 0

Risposto
Compose High Level Synthesis (HLS) from Matlab code
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

oltre 4 anni fa | 0

Risposto
How to use Matlab generated c code for High Level Synthesis ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

oltre 4 anni fa | 0

Risposto
Generate C code for HLS?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

oltre 4 anni fa | 1

Risposto
How to add a custom parameter in the generated module with HDL Coder,simulink?
How are generics supported in HDL Coder? https://www.mathworks.com/support/search.html/answers/382489-how-are-generics-supporte...

oltre 4 anni fa | 0

| accettato

Risposto
HDL Code generation and deploy data onto the hardware board
For #1 Getting Started with Targeting Xilinx Zynq Platform https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-ha...

oltre 4 anni fa | 0

Risposto
HDL code generation of delay block and problem in regard to the use of verilog ce_out
A sample model would be helpful. I built one using the info shown in the picture above. Given there is a ratio of 5000 bet...

oltre 4 anni fa | 1

| accettato

Risposto
In HDL Simulink, How to convert from integer to boolean array.
https://www.mathworks.com/help/hdlcoder/ref/bitslice.html >> hdlcoder_int2bits_bits2int You can check this thread as well....

oltre 4 anni fa | 0

Risposto
HDL supported block for integer to binary
can you try this example? >>hdlcoder_int2bits_bits2int

oltre 4 anni fa | 0

Risposto
Update Diagram fails on "No Connect" Cosim block
Can you share a sample model with your usecase?

oltre 4 anni fa | 0

Risposto
How to deploy matlab deep learning models to Texas Instruments?
DL code generated for library-free “none” target should be deployable on TI C2000. https://www.mathworks.com/videos/generate-...

oltre 4 anni fa | 0

| accettato

Risposto
Vivado 2020.2 and HDL coder
HDL Coder generated VHDL/Verilog code is Vivado version independent and works with any version of the Xilinx software. For Viva...

oltre 4 anni fa | 1

| accettato

Risposto
Timing Constraint not met error for ZYNQ706
You can consider pipelining the design. See the timing related optimization section in HDL Coder https://www.mathworks.com/help/...

oltre 4 anni fa | 0

Risposto
Numerator of FIR filter using "firpm" command is not working properly for ZYNQ 706
If your Simulink model has a testbench you can consider generating HDL code with the testbench and verify the generated code in ...

oltre 4 anni fa | 0

Risposto
Colon operation in fixed-point
Support for colon exists with fixed-point types according to documentation. https://www.mathworks.com/help/fixedpoint/ref/colon....

oltre 4 anni fa | 0

Risposto
how to fix inferring latch(es) for signal or variable holds its previous value in one or more paths through the process vhdl error
This could be a bug in code generation process. Can you reach out to https://www.mathworks.com/support.html?

oltre 4 anni fa | 0

Risposto
Colon operation in fixed-point
MATLAB HDL Coder workflow does support colon operator during fixed-point conversion and code generation. Please share a sample d...

oltre 4 anni fa | 0

Risposto
SIMPLE HDL code generation example
This example should help do basic LED blinking using a simple counter. Getting Started with Targeting Xilinx Zynq Platform ope...

oltre 4 anni fa | 0

Risposto
Error while generating HDL code from Matlab: Invalid data type. H must be double.
Can you share your design.m, testbench.m files and the project file with necessary settings? Thanks

oltre 4 anni fa | 0

Risposto
Connection Failed in hardware setup
https://www.mathworks.com/support.html Please reach out to support team on this topic.

oltre 4 anni fa | 0

Risposto
i m trying using converting signal processing block into hdl code , but some of the blocks are not compatible into hdl conversion .does anyone knows how to do it
https://www.mathworks.com/help/radar/ug/automotive-adaptive-cruise-control-using-fmcw-and-mfsk-technology.html This example is ...

oltre 4 anni fa | 0

Risposto
error after targheting xilinx Virtex UltraScale+ VCU118.
Possible pilot error in setting up the custom reference design or board support package. Please contact https://www.mathworks.c...

oltre 4 anni fa | 0

Risposto
Why do I receive error Output argument "file_name" (and maybe others) not assigned during call to "mdlAdv_Scripts_Run.get_config_file"
I couldn't find the class/structure mdlAdv_Scripts_Run and method/member get_config_file in HDL Workflow Advisor. Guessing poss...

oltre 4 anni fa | 0

Risposto
HDL IP Core generation for Xilinx Vivado fails since the year turned from 2021 to 2022
HDL IP core generation using Xilinx Vivado fails as of January 1, 2022 (2656440) https://www.mathworks.com/support/bugreports/2...

oltre 4 anni fa | 1

Carica altro