Risposto
How can I call filter coefficients in bit reversed order for HDL FFT?
This question can best addressed by Vivado System Generator support team at https://www.xilinx.com

oltre 4 anni fa | 0

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How to generate Verilog code from Deep Learning Network in MATLAB?
Deep Learning Processor Customization and IP Generation Configure, build, and generate custom bitstreams and processor IP cores...

oltre 4 anni fa | 0

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HDL synthesis doen't end?
It is possible you have very high resource usage or timing issue with your generated code. You should consider using high leve...

quasi 5 anni fa | 0

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How can I force HDL Coder to use DSP48 slices?
if you are looking to automate DSP usage improvements you can consider using Synthesis Attributes or features like Adaptive pipe...

quasi 5 anni fa | 0

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How to update template on multiple Simulink models (programmatically)?
https://www.mathworks.com/help/hdlcoder/ug/hdl-coder-simulink-templates.html Use Simulink Templates for HDL Code Generation HD...

quasi 5 anni fa | 0

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IP core generation zedboard FMCOMMS2 gives 2 critical warning in Vivado
web(fullfile(docroot, 'hdlcoder/ug/hdlqpsktransmitterandreceiver.html?s_tid=doc_srchtitle'))

quasi 5 anni fa | 0

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Can I use a IFFT HDL Optimized block with an input length greater than 2^16?
https://www.mathworks.com/help/dsp/ref/dsp.hdlfft-system-object.html FFT length — Number of data points used for one FFT calcul...

quasi 5 anni fa | 0

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Issues: FIR filter by HDL Coder on Redpitaya platform
>> mlhdlc_demo_setup('sfir')

quasi 5 anni fa | 0

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Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
https://www.mathworks.com/help/hdlcoder/ug/using-xilinx-system-generator-for-dsp-with-hdl-coder.html

quasi 5 anni fa | 0

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results of HDL streaming FFT block is not same as FFt block in dsp toolbox
dsp.HDLFFT is optimized for HDL Code generation. dsp.HDLFFT Fast Fourier transform — optimized for HDL code generation The H...

quasi 5 anni fa | 0

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Potential Bugs in R2014b HDL Coder ('hdlcoder_slsysgen')
https://www.mathworks.com/help/hdlcoder/ug/using-xilinx-system-generator-for-dsp-with-hdl-coder.html

quasi 5 anni fa | 0

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Generating higher sampling frequency
Using Oversampling Factor and Latency Strategy The Oversampling factor (HDL Coder) specifies the factor by which the FPGA clock...

quasi 5 anni fa | 0

Risposto
GPU: Audio DSP
https://www.mathworks.com/help/hdlcoder/ug/running-an-audio-filter-on-live-audio-input-using-a-zynq-board.html

quasi 5 anni fa | 0

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Risposto
Can Matlab R2018b use the Kintex7 board from a X310 USRP and, if so, how?
https://www.mathworks.com/hardware-support/usrp.html

quasi 5 anni fa | 0

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FPGA: Audio DSP
Running an Audio Filter on Live Audio Input Using a Zynq Board This example shows how to model an audio system and implement it...

quasi 5 anni fa | 0

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Error while converting a sine PWM block in simulink to HDL code
See the attached example on how to generate square wave pulses at regular intervals. The waveform parameters, Amplitude, Pulse W...

quasi 5 anni fa | 0

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Error while converting a sine PWM block in simulink to HDL code

quasi 5 anni fa | 0

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Having issues with connecting Zynq zedboard to computer
web(fullfile(docroot, 'hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html'))

quasi 5 anni fa | 0

Risposto
I want to know about the resource utilization on a FPGA when using FFT HDL code generated by HDL coder application on MATLAB.
web(fullfile(docroot, 'dsp/ref/ffthdloptimized.html?s_tid=doc_ta')) Check Performance section

quasi 5 anni fa | 0

Risposto
How does it work the AXI4 Stream IIO driver?
web(fullfile(docroot, 'hdlcoder/ug/getting-started-with-axi4-stream-interface-in-zynq-workflow.html?s_tid=doc_srchtitle')) we...

quasi 5 anni fa | 0

Risposto
Best Practices for Simulink HDL Coder Development
https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-guide HDL Coder Evaluation Referenc...

quasi 5 anni fa | 0

Risposto
HDL Coder (2014b) fixed point division RoundMode error
Consider using hdlfimath when generating HDL code from MATLAB with fixed-point. >> hdlfimath

quasi 5 anni fa | 0

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Does HDL coder from Simulink support AXI-4 Stream Interface for Xilinx Zynq?
Getting Started with AXI4-Stream Interface in Zynq Workflow This example uses: HDL Coder DSP System Toolbox Embedded Coder...

quasi 5 anni fa | 0

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Strange behavior of HDL coder when generating resettable register
Synchronous Subsystem Behavior with the State Control Block What Is a State Control Block? When you have blocks with state, ...

quasi 5 anni fa | 0

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I have the following errors when I run HDL coder in MATLAB 2013a ?errors in fixed point conversion
This is an unexpected internal error during fixed-point conversion. The issue occurs during verification step of generated fixed...

quasi 5 anni fa | 0

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How to prepare FPGA board for MATLAB
You would need license to HDL Coder. See third party tool requirements for HDL Coder in this page. web(fullfile(docroot, 'hdlc...

quasi 5 anni fa | 0

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Is it possible to purge Simulink Model?
attached sample file can be extended to purge whatever cruft you have in your session. >> purgesession Purging slprj Purging ...

quasi 5 anni fa | 0

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Simulation of matlab generated vhdl code leads to Errors
HDL Coder handles MATLAB one based indexing and converts the logic to zero based indexing when generating VHDL / Verilog code. ...

quasi 5 anni fa | 0

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HDL Coder with Xilinx Sysgen R2013b
Using Xilinx® System Generator for DSP with HDL Coder™ This example shows how to use Xilinx System Generator for DSP with HDL C...

quasi 5 anni fa | 0

Risposto
Hi sir i am working on hdl coder and i am new to it and my pbm is have written the matlab code and compiled it sucessfully, even generated hdl code but in hdl test bench i am not getting the exact ans( matlab output and hdl output not matching).
HDL Coder generates bit true and cycle accurate code corresponding to the design. The testbench captures the stimulus and respon...

quasi 5 anni fa | 0