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hdl coder supported in Cyclone 10 LP from Intel.
HDLCoder generates code targetable for all Intel FPGA families including Cyclone 10. https://www.mathworks.com/products/hdl-co...

quasi 6 anni fa | 0

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Evaluation of elaborate function error in HDL coder
This is an unexpected error from HDLCoder. Will it be possible to share the model? We can evaluate and provide the workaround. ...

quasi 6 anni fa | 0

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Implementation Latency of Blackbox Subsystem when using oversampling
Hi Dominque, Is it possible to share a mockup model with the basic configuration of doc block based blackbox as you describe an...

quasi 6 anni fa | 0

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FFT HDL Optimized for HDL Coder(When generate RTL Code and Testbench,occur error:)
This is an unexpected internal error. I believe it is fixed in subsequent release. By any chance are you using a reciprocal of s...

quasi 6 anni fa | 0

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Error in Simulink Model: "Error in hdl.serializer 1D/getOutputSizeS: Index exceeds the number of array elements (0)"
Hi Samuel, We are not aware of this issue. Can you share your model and reproduction steps? Thanks

quasi 6 anni fa | 0

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How to implement periodogram block in HDL coder?
Happy to consider this suggestion. May I know your application using periodogram on asic/fpga?

quasi 6 anni fa | 0

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How to generate a fixed point HDL Code from a Simscape Electrical model ?
Typically fixed-point conversion leads significant numerical challenges on this model due to large dynamic ranges of the state-s...

quasi 6 anni fa | 0

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'vsim' requires HDL Verifier.
Are you just trying to launch Qeustasim from within MATLAB? You should try this command in MATLAB to launch the executable from...

quasi 6 anni fa | 1

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[HDL Coder] Bug: Fixed point converter does not descend into System Objects
Unfortunately the development team cannot reproduce the issue. Is it possible the attached reproduction steps are not sufficient...

quasi 6 anni fa | 0

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Can I generate HDL Code for models with Xilinx System Generator blocks?
While running the simulation using the TCL script generated by HDL Coder, HDL Coder generates SysGen_with_HDL_Coder_CustomTCL_ru...

quasi 6 anni fa | 0

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Can I generate HDL Code for models with Xilinx System Generator blocks?
If you have access to R2018a can you try to reproduce the issue in that release? We suspect this is already resolved in 18a rele...

quasi 6 anni fa | 0

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How can I convert MATLAB Code to VHDL Code?
https://www.mathworks.com/products/hdl-coder.html HDL CoderTM generates portable, synthesizable Verilog® and VHDL® code from ...

quasi 6 anni fa | 0

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VHDL Coder Error: "Found an unsupported unbounded loop structure"
It looks like the error is originating from the unsupported functions calls on these lines. HDLCoder team is aware of the i...

quasi 6 anni fa | 1

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Can we import any schematic Xilinx Vivado to MATLAB Simulink
>> help importhdl importhdl Import HDL code (Verilog) and generate Simulink model. Can this feature help your usecase? Tha...

quasi 6 anni fa | 0

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Can we convert a HDL code into MATLAB code directly in MATLAB
You can import your verilog module to Simulink. Will this be of help? >> help importhdl importhdl Import HDL code (Verilog)...

quasi 6 anni fa | 0

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Can anybody help me to convert 2018b simulink model file to 2015b simulink model file?
I am attaching models exported to 15b. You may need a bit more work on the model. Please replace the block with your version in ...

quasi 6 anni fa | 0

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VHDL Coder Error: "Found an unsupported unbounded loop structure"
Typically this error means you have loop bounds that are not static and determinable at compile time. Compiling MATLAB functions...

quasi 6 anni fa | 0

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Generating HDL code error in the example "HDL Optimized QPSK Receiver with Captured Data"
This is a bug in HDL test bench generation. Please reach out to support@mathworks.com with reproduction steps.

quasi 6 anni fa | 0

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HDL Coder with error but empty Build Log
This looks like C compiler bug when compiling the MATLAB generated C code to create mex file. Can you please share reproduction ...

quasi 6 anni fa | 0

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How do I generate HDL code from a masked subsystem that is not at the model's root level in Simulink?
This limitation is now resolved in the upcoming 20b pre-release of HDLCoder.

quasi 6 anni fa | 0

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Possible to generate HDL from 5G Toolbox Code?
Please refer to product documentation here that could be of help. https://www.mathworks.com/products/lte-hdl.html

quasi 6 anni fa | 1

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CIC compensation hdl generation error
Thanks for the model. I believe the block is not supported for HDL code generation. Please contact support@mathworks.com for the...

quasi 6 anni fa | 0

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IFFT HDL optimizer block to HDL coder conversion
Based on the description of the issue this may already resolved in latest version of MathWorks. Please reach out to support@math...

quasi 6 anni fa | 0

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CIC compensation hdl generation error
I cannot generate HDL from the attached model and reproduce the error? Can you attach the correct version of the model? Thank yo...

quasi 6 anni fa | 0

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IFFT HDL optimizer block to HDL coder conversion
Can you provide us a sample example and the version of MATLAB you are using?

quasi 6 anni fa | 0

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[HDL Coder]: BUG?/ Function Location missing in Error Report -> find variable by name?
We got to compile the snippet in Simulink using MATLAB function block, looking into the standalone MATLAB issue. Thanks for repo...

quasi 6 anni fa | 0

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[HDL Coder]: BUG?/ Function Location missing in Error Report -> find variable by name?
MATLAB code with variable dimensions in MATLAB is not suitable for mapping to hardware. Noting the enhancement to improve the er...

quasi 6 anni fa | 0

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hdl coder error when compiling stateflow
Can you attach a small version of the model to reproduce the error? "Enumerated name 'IN_NO_ACTIVE_CHILD' is present in types ...

quasi 6 anni fa | 0

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HDL Coder reset - asynchronous and synchronous possible?
Currently it is not possible. The generated code uses either sync or async reset. Can you explain your usecase? Thanks

quasi 6 anni fa | 0

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How can I modify mapping options in HDL Workflow Advisor in Simulink?
After code generation HDLCoder creates a Vivado Project and configures the project with generated files. You should see a link t...

quasi 6 anni fa | 0

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