Risposto
Synthesize Matlab function with large input and output onto FPGA
You have a large IO design (in frames); the design needs conversion to samples. Prior to R2022b release there was no automation ...

oltre 2 anni fa | 0

Risposto
Can't generate Simulink model from Simulink function block
https://www.mathworks.com/help/hdlcoder/ug/hdl-optimizations-across-matlab-function-simulink-blocks.html You can convert a subs...

oltre 2 anni fa | 0

Risposto
How to read a matrix data from a subfunction by HDLs coder
https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-and-examples HDLCoder Design Patterns and E...

oltre 2 anni fa | 0

Risposto
how to configure parameters for NCO(frequency shifting or frequency correction) simulink block set based on the NCO operation has performed in the matlab script
Please find attached a sample NCO block that can generate HDL code.

oltre 2 anni fa | 0

| accettato

Risposto
Deep Learning HDL Toolbox - Error using dnnfpga.compiler.codegenfpga Index exceeds the number of array elements. Index must not exceed 0.
This is not an expected error message. Please reach out to tech support for help and any available workaround.

oltre 2 anni fa | 0

Risposto
Error when converting design from Matlab Simulink to HDL
The model has an incorrect/undefined type specification. You need to use the fixdt(1,64,32) syntax. In addition, please n...

oltre 2 anni fa | 0

Risposto
HDL "complex to Magnitude and angle" module show critical path which can not meet 160MHz clock timing
Would you be able to share your model and HDL Coder code generation steps to reproduce the workflow?

oltre 2 anni fa | 0

Risposto
HDL Workflow Advisor - Step 3.2 - "Failed Index exceeds the number of array elements. Index must not exceed 2" in hdlturnkey.interface.ChannelBased/connectFrameInterfacePort
This is not an expected error message. Please reach out to tech support with reproduction steps.

oltre 2 anni fa | 1

Risposto
Converting Simulink Bus with mixed datatypes to an array of doubles
Can you share your current workaround? I wonder if this block would be of help in your usecase. Bus to Vector https://www.math...

oltre 2 anni fa | 0

Risposto
Simulink HDL Coder & Vitis Model Composer cannot find the same Device
Model Composer library in Simulink needs Vitis workflows to generate HDL Code. https://www.xilinx.com/products/design-tools/vit...

oltre 2 anni fa | 0

Risposto
How to initialize Dual rate Dual port ram?
RAM System object can be used as a block in Simulink and it supports Initial Value. The HDL library browser that ships with ...

oltre 2 anni fa | 0

Risposto
Why did I receive an error messageļ¼šISim engine error: Failed to Load up XSI.
Please try running with Vivado 2022.1. You can see our supported software in the documentation at: https://www.mathworks.com/hel...

oltre 2 anni fa | 0

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Inviato


HDLCoder Design Patterns and Examples
Several tutorials in this submission show how to generate HDL from MATLAB code, Simulink models, and Simscape models.

oltre 2 anni fa | 5 download |

4.7 / 5

Risposto
Simulink port annotations do not appear with HDL definition of wire/reg
I have reported the issue to the development team. As a workaround consider right-cliking on the port, choose port propert...

oltre 2 anni fa | 0

| accettato

Risposto
How ro restore a fixed-pointed and saved model to its unfixed state?
>>I want to change some fuctions on its unfixed state. Do you mean the restore step in the Fixed-Point Tool failed for you a...

oltre 2 anni fa | 0

Risposto
DSP Builder HDL Import Design Example error
Please reach out to tech support. The error is coming from HDL Cosimulation block (probably you are using a HDL Verifer Cosimu...

oltre 2 anni fa | 0

Risposto
ip core generation stuck at hdl code generation step
Would you be able to share the MATLAB Code and the Project file? Please reach out to tech support for help.

oltre 2 anni fa | 0

Risposto
HDL Coder, Assertion failed: B:\matlab\src\cgir_hdl\dom_pir_core\dutinfo.cpp:101:portIdx < m_inportMap.size()
Can you share the model? This is not an expected error. Please reach out to MathWorks tech support and they can help you with ...

oltre 2 anni fa | 0

Risposto
implementing complex multiplication in simulink
For HDL Code Generation you can use the Simulink and MATLAB function examples shown below. These examples use FPGA/ASIC fri...

oltre 2 anni fa | 1

Risposto
HDL Coder cannot run HDL Code Generation
If you want to run a set of steps you need to right-click on the step and run to the task. It will run all the steps leading...

oltre 2 anni fa | 1

Risposto
How to generate testbench for a model whose input signals come from matlab workspace?
"Generate HDL Testbench" works on a subsystem with some stimulus and response and not the whole model. Mark the DUT "model/sub...

oltre 2 anni fa | 1

| accettato

Risposto
When I try to check Subsystem Compatibility, the report says"cannot coonect to model, please try Update Diagram".
The error message is showing that during code generation process, HDL Coder is unable to compile the model. If you are able to ...

oltre 2 anni fa | 0

| accettato

Risposto
HDL Workflow Advisor Error
If you can share the model please add the attachment. If open the Sample time legend and do not see continuous sample time (0) f...

quasi 3 anni fa | 0

Risposto
Error - periodic sample time - Pixels to Frame
The pixelIn and controlIn should be operating at the same rate when using pixel streaming based interface. https://www.mathwo...

quasi 3 anni fa | 0

Risposto
HDL Workflow Adviser Error: Abnormal exit: Invalid Simulink object name: stateflow
This error is unrelated to the name of the chart. Probably a corrupt model or an internal issue during HDL Code generation. If...

quasi 3 anni fa | 0

Risposto
HDL Code Generation Check Report - word width error
You have to constrain the operator wordlength to be within 128 bit limit for HDL Code generation.

quasi 3 anni fa | 0

Risposto
How to use proprietary IPS with HDL coder?
When generating RTL from Simulink model or MATLAB algorithm, there are several ways to integrate custom HDL IP with HDL Coder ge...

quasi 3 anni fa | 0

Risposto
design and implement adaptive filter for noise signals cancellation in ecg and heartbeat
https://www.mathworks.com/matlabcentral/fileexchange/35328-simulink-model-for-fetal-ecg-extraction-hdl-compatible-algorithm

quasi 3 anni fa | 0

Risposto
Error Cannot find a valid sample time for the model. Continuous signal rates are not supported in native floating-point mode.
This is error is auto-resolved in HDL Coder starting R2023a release. https://www.mathworks.com/help/hdlcoder/release-notes.htm...

quasi 3 anni fa | 1

Risposto
Error in converting function into fixed point using HDL Coder
Getting Started with Targeting Xilinx Zynq Platform This example shows how to use the hardware-software co-design workflow to b...

quasi 3 anni fa | 0

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