Add 'MARK_DEBUG = "TRUE"' to signals in generated HDL

I need to mark certain signals in a verilog code generation with the attribute MARK_DEBUG = "TRUE",

for example:

(* MARK_DEBUG = "TRUE" *) wire [15:0] snapshot_addr; // uint16

How do I do this?

Many thanks, Kevin

Answer 1

[Kiran Kintali]

Currently synthesis attribute specification is limited to certain blocks like product block.

This capability is planned for ports, signals, subsystems and more blocks in the near future releases.

Please reach out to tech support for additional requests in this area.