Real Reciprocal Square Root HDL Optimized

R2026b

Compute reciprocal of square root of real input and generate optimized HDL code

Since R2026b

• 

Real Reciprocal Square Root HDL Optimized block

To add a block to a model, double-click the canvas and start typing the block name. Then, select the block from the list.

Libraries:
Fixed-Point Designer HDL Support / Math Operations

Description

The Real Reciprocal Square Root HDL Optimized block computes y such that y = 1/sqrt(abs(u)).

Examples

How to Use Real Reciprocal Square Root HDL Optimized Block

The Real Reciprocal Square Root HDL Optimized block uses a lookup table and linear interpolation to compute the reciprocal square root of the absolute value of a real-valued input.

I/O Interface

The Real Reciprocal Square Root HDL Optimized block uses a fully parallel architecture. The block can accept input data on any cycle, including on consecutive clock cycles. Use the validIn port to indicate a valid input. When the block has finished the computation, the validOut port outputs true for one clock cycle. For valid inputs sent on consecutive clock cycles, validOut is also set to true on consecutive clock cycles.

Define Input Data and Simulation Parameters

To set up the model for simulation, define input data, input data type, and output data type.

Select the input data type: fixed, scaledDouble, single, or double.

DT = 'fixed';

For a fixed-point data type, specify the input word length, fraction length, and output data type.

inputWordLength = 16;
inputFractionLength = 10;
InputType = numerictype(1,inputWordLength,inputFractionLength);
OutputType = fixdt(1,27,20);

Generate random input data u. Ensure the input data contains at least one 0 value to demonstrate block behavior for division by zero.

rng('default');
numSamples = 10;
u = randn(1,numSamples);
u(2) = 0;

Cast the input data u to the selected input data type. If the input is floating point, set the output data type to floating point.

switch lower(DT)
    case 'fixed'
        u = cast(u,'like',fi([],InputType));
    case 'scaleddouble'
        u = cast(u,'like',fi([],InputType,'DataType','ScaledDouble'));
        OutputType = numerictype(OutputType,'DataType','ScaledDouble');
    case 'single'
        u = single(u);
        OutputType = 'single';
    case 'double'
        u = double(u);
        OutputType = 'double';
    otherwise
        u = double(u);
        OutputType = 'double';
end

Open and Simulate Model

Open the RealReciprocalSqrtModel model.

model = 'RealReciprocalSqrtModel';
open_system(model);

Configure the model workspace and run the simulation.

fixed.example.setModelWorkspace(model,'u',u,'numSamples',numSamples,'OutputType',OutputType);
out = sim(model);

Verify Output Solutions

Verify the output solutions returned by the Real Reciprocal Square Root HDL Optimized block.

Compare the fixed-point result from the Real Reciprocal Square Root HDL Optimized block to the floating-point result from the MATLAB divide and square root functions.

Verify the relative error is smaller than the estimated upperbound except for the division by zero case.

y = out.y(1:numSamples)';
u_nonzero = real(double(u(u~=0)));
y_nonzero = real(double(y(u~=0)));
yBuiltIn = 1./sqrt(abs(u_nonzero));

if isfi(u)&&isfixed(u)
    iIn = u.WordLength-u.FractionLength-issigned(u);
    relTolUpperbound = 2^max([-19,ceil(iIn/2)-OutputType.FractionLength+1]);
else
    relTolUpperbound = double(cast(max(sqrt(double(eps(u(:))))),'like',y));
end

Check if any relative error is greater than the estimated error upper bound.

relError = abs((double(y_nonzero)-yBuiltIn)./yBuiltIn);
if any(relError > relTolUpperbound)
    warning('numeric error exceeds estimated upper bound by %f',relError-relTolUpperbound);
end

Verify that when the input is 0, the output value is the upperbound of the specified output data type and that the division by zero flag returns true.

dbzFlagCorrect = find(u==0)==find(out.dbz==true)

dbzFlagCorrect = logical
   1

if isfi(u)
    dbzValueCorrect = y(out.dbz==true) == upperbound(numerictype(OutputType))
else
    dbzOutput = y(out.dbz==true)
end

dbzValueCorrect = logical
   1

If the input is fixed point, verify that the output is bit-exact with the MATLAB function equivalent, embblk.realReciprocalSqrt.

if isfi(u)&&isfixed(u)
    yMATLAB = embblk.realReciprocalSqrt(u,OutputType);
    bitExactWithMLTwin = ispropequal(y,yMATLAB)
end

bitExactWithMLTwin = logical
   1

Block Latency

The block latency is defined as the number of clock cycles between a successful input and when the corresponding output becomes valid. The latency of this block depends on the data type of the input.

if isfi(u)
    explatency = (u.WordLength > 9)*2 + issigned(u) + 5 + max(nextpow2(u.WordLength) - 3,0)
else
    explatency = 0
end

explatency = 
9

Retrieve block latency from the simulation.

tDataIn = find(out.logsout.get('validIn').Values.Data == 1);
tDataOut = find(out.logsout.get('validOut').Values.Data == 1);
actualLatency = tDataOut(1:numSamples) - tDataIn(1:numSamples);
actualLatency = actualLatency(1)

actualLatency = 
10

Ports

Input

u — Value to take reciprocal square root of

scalar | vector | matrix | multidimensional array

Value to take the reciprocal square root of, specified as a real-valued scalar, vector, matrix, or multidimensional array. If the input is a negative value, the block computes the reciprocal square root of the absolute value of the input.

Slope-bias representation is not supported for fixed-point data types.

Data Types: single | double | fixed point

validIn — Whether input is valid

scalar

Whether input is valid, specified as a Boolean scalar. This control signal indicates when the data from the u input port is valid. When this value is 1 (true), the block captures the value at the u input port. When this value is 0 (false), the block ignores the input samples.

Data Types: Boolean

Output

y — Reciprocal square root

scalar | vector | matrix | multidimensional array

Reciprocal square root, returned as a real scalar, vector, or matrix of the same dimension as input u and with the data type specified by the Output datatype parameter.

Data Types: single | double | fixed point

divideByZero — Whether value at output port is result of division by zero

scalar | vector | matrix

Whether the value at the y output port is the result of a division by zero operation, returned as a Boolean scalar, vector, or matrix of the same dimension as input u. When the value of this signal is 1 (true), the corresponding output value at the y port is the result of division by zero. When the value of this signal is 0 (false), the corresponding output value at the y port is the result of division by a nonzero value.

Dependencies

To enable this port, select the Show divide by zero port parameter.

Data Types: Boolean

validOut — Whether output data is valid

scalar

Whether output data is valid, returned as a Boolean scalar. When the value of this control signal is 1 (true), the block has successfully computed the output at port y. When this value is 0 (false), the output data is not valid.

Data Types: Boolean

Parameters

To edit block parameters interactively, use the Property Inspector. From the Simulink^® Toolstrip, on the Simulation tab, in the Prepare gallery, select Property Inspector.

Output datatype — Data type of output

fixdt(1,18,10) (default) | single | double | fixdt(1,16,0) | <data type expression>

Data type of output port y, specified as fixdt(1,18,10), single, double, fixdt(1,16,0), or as user-specified data type expression. The type can be specified directly or expressed as a data type object, such as Simulink.NumericType.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

Parameter:	OutputType
Values:	fixdt(1,18,10) (default) | single | double | fixdt(1,16,0) | <data type expression>
Data Types:	char | string

Example: set_param(gcb,"OutputType","fixdt(1,16,0)")

Show divide by zero port — Whether to show divideByZero port

off (default) | on

Select this parameter to show the divideByZero port.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

Parameter:	dbzPort
Values:	0 (false) (default) | 1 (true)
Data Types:	logical

Example: set_param(gcb,"dbzPort",1)

Tips

• The output of the Real Reciprocal Square Root HDL Optimized block is bit-exact to the embblk.realReciprocalSqrt function for binary-point scaled fixed-point data types.

Algorithms

Approximation of Reciprocal Square Root

This block implements a counting leading zeros (CLZ) based normalizer and a lookup table approximation of the reciprocal square root operation with linear interpolation between breakpoints. The lookup table size is less than or equal to 36 Kb. If the input word length is less than 10 bits, the block implements a direct lookup table without interpolation.

Precision

The precision of the approximation method is defined as the estimated relative error upper bound: log₂(E_relative) = max(-19, ceil(i_in/2) - f_out + 2), where:

• i_in = input type integer length

• f_out = OutputType fraction length

The precision of this block is bounded to a maximum relative error of 2^-19. The precision is also limited by the input integer length and the output fraction length, due to the nature of the reciprocal operation. A larger input results in a smaller output, such that more input integer bits require more output fraction bits.

Latency

The latency of the Real Reciprocal Square Root HDL Optimized block is defined from the input to the corresponding output. The latency of the block depends on the input data type, as summarized in the table.

Input Type	Latency
Fixed point or scaled double fi	(u.WordLength > 9)*3+issigned(u)+5+max(nextpow2(u.WordLength)-3,0)
Floating point	0

For quick reference, this table provides latency of the block for a given input word length and signedness.

Input Word Length	Latency of Unsigned Input	Latency of Signed Input
<= 8 bits	5	6
9 bits	6	7
>= 10 bits	nextpow2(u.WordLength) + 5	nextpow2(u.WordLength) + 6

How to Interface with the Real Reciprocal Square Root HDL Optimized Block

Because of its fully pipelined nature, the Real Reciprocal Square Root HDL Optimized block is able to accept input data on any cycle, including consecutive clock cycles. To send input data to the block, the validIn signal must be true. When the block has finished the computation and is ready to send the output, it will change validOut to true for one clock cycle. For inputs set of consecutive cycles, validOut will also be set to true on consecutive cycles.

Hardware Resource Utilization

This block supports HDL code generation using the Simulink HDL Workflow Advisor. For an example, see HDL Code Generation and FPGA Synthesis from Simulink Model (HDL Coder) and Implement Digital Downconverter for FPGA (DSP HDL Toolbox).

This example data was generated by synthesizing the block on an AMD^® Zynq^® ZC706 evaluation kit. The synthesis tool was Vivado^® v2025.1.1.

These parameters were used for synthesis:

• Input data type — fixdt(1,16,10)

• Output data type — fixdt(1,27,20)

Resource	Usage	Available	Utilization (%)
Slice LUTs	229	218600	0.10
Slice Registers	199	437200	0.05
DSPs	1	900	0.11
Block RAM Tile	1	545	0.18
URAM	0	0

	Value
Requirement	3.3333 ns (300 MHz)
Data Path Delay	2.219 ns
Slack	1.046 ns
Clock Frequency	437.19 MHz

Division by Zero Behavior

When the input u is 0 and has a fixed-point data type, then the output y is equal to upperbound(Output datatype).

For floating-point inputs, the Real Reciprocal Square Root HDL Optimized block follows IEEE^® Standard 754.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Slope-bias representation is not supported for fixed-point data types.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
FlattenHierarchy	Removes Real Reciprocal Square Root HDL Optimized block hierarchy from generated HDL code. The default is inherit. See also FlattenHierarchy (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes (HDL Coder).

Restrictions

Supports fixed-point data types only.

Version History

Introduced in R2026b