addAXI4SlaveInterface
Write data to IP core or read data from IP core using AXI4 or AXI4-Lite interface
Since R2020b
Description
addAXI4SlaveInterface(
adds an AXI4 slave interface that you can use to control the DUT
ports mapped to AXI4 or AXI4-Lite interfaces in the HDL Coder™ generated IP core from MATLAB®.hFPGA
)
addAXI4SlaveInterface(
adds an AXI4 slave interface that you can use to control the DUT
ports mapped to AXI4 or AXI4-Lite interfaces in the HDL Coder generated IP core from MATLAB, with one or more properties specified as name-value pair arguments. Enclose
each property and value pair in single quotes.hFPGA
, Name,Value
)
Examples
Input Arguments
Name-Value Arguments
Version History
Introduced in R2020b