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Clock-rate pipelining

Insert pipeline registers at a clock rate that is faster than the data rate

Model Configuration Pane: Optimization / Pipelining


If your design contains multicycle paths, use clock-rate pipelining to insert pipeline registers at a clock rate that is faster than the data rate. This optimization improves the clock frequency and reduces the area usage without introducing additional latency. Clock-rate pipelining does not affect existing design delays in your model. It is an alternative to using multicycle path constraints with your synthesis tool.


If you specify an Oversampling factor greater than one or select Treat Simulink rates as actual hardware rates, make sure that you select the Clock-rate pipelining check box. Clock-rate pipelining identifies regions in your model that run at the same slow data rate and are delimited by Delay blocks or blocks that introduce a rate transition. The code generator converts these regions to the faster clock rate by introducing Repeat blocks at the input of the region and Rate Transition blocks at the output of the region.


On (default) | Off

Insert pipeline registers at the clock rate for multi-cycle paths.


Insert pipeline registers at the data rate for multi-cycle paths.


To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the ClockRatePipelining setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.


Recommended Settings

No recommendations.

Programmatic Use

Parameter: ClockRatePipelining
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Version History

Introduced in R2014b