Divide

Implement control-signal-based division operation

Since R2020b

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Description

The Divide block performs the division operation on the input data signals. The block has control signals that indicate whether the input and output data are valid. You can also specify the number of iterations of the algorithm and the latency strategy.

To use this block in your Simulink^® model, open the HDLMathLib library by entering this command in the MATLAB^® Command Window:

open_system("HDLMathLib")

Latency Considerations

You can simulate the Divide block with latency. This block is a masked subsystem that contains the LumpLatency MATLAB Function block. The subsystem uses this MATLAB Function block to compute the latency based on the input and output data types. The software calculates the latency of the block using the word length and fractional length of fixed-point input and output.

The block supports three latency modes. You can specify a custom latency value by setting the Latency Strategy parameter to Custom.

To view the function that computes the latency of the block, open the LumpLatency block in the masked subsystem. To view inside the mask, click the ⇩ icon on the block. For more information, see Lump Latency for Divide Block.

Examples

Implement Divide Block with Control Signals

Implement the control-signal based Divide block and use it to generate HDL code.

• Open Script

Limitations

The block has these limitations:

• Does not support floating-point data types, such as half, single, and double.

• Cannot be used in Synchronous Subsystem.

• Does not support resource sharing optimization.

Ports

Input

dividendDataIn — Dividend input signal

scalar | vector

Dividend input to calculate the division.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | bus

divisorDataIn — Divisor input signal

scalar | vector

Divisor input to calculate the division.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | bus

validIn — Indication of whether input control signal is valid

scalar

Input control signal that indicates whether the input signal is valid.

Data Types: Boolean

Output

dataOut — Output data signal

scalar | vector

Output signal that is the division of the dividend and divisor input signals.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | bus

validOut — Indication of whether output control signal is valid

scalar

Output control signal that indicates whether output signal is valid.

Data Types: Boolean

Parameters

Latency strategy — Latency strategy

Max (default) | Min | Custom | Zero

Specify whether to map the blocks in your design to minimum, maximum, custom, or zero latency. For more information, see LatencyStrategy.

Programmatic Use

Block Parameter: latencyMode

Type: character vector

Values: 'Max' | 'Min' | 'Custom' | 'Zero'

Default: 'Max'

Custom latency — Custom latency value

0 (default)

When you set Latency strategy to Custom, use this parameter to specify the custom latency value. The latency must be a nonnegative integer in the range [0, L], where L is the maximum latency value of Divide block. For more information, see CustomLatency.

Dependency

To use this parameter, set Latency strategy to Custom.

Programmatic Use

Block Parameter: customLatencyValue

Type: Integer

Values: 0 to Max latency

Default: 0

Output data type — Output data type

Inherit: Inherit via internal rule (default) | Inherit: Same as first input | Inherit: Inherit via back propagation | Inherit: Keep MSB | Inherit: Match Scaling | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 | fixdt(1,16) | fixdt(1,16,0) | <data type expression>

Specify the output data type. The data type can be inherited or specified directly.

Programmatic Use

Block Parameter: OutDataTypeStr

Type: character vector

Values: 'Inherit: Inherit via internal rule' | 'Inherit: Inherit via back propagation' | 'Inherit: Same as first input' | 'Inherit: Keep MSB' | 'Inherit: Match Scaling' | 'int8' | 'uint8' | int16 | 'uint16' | 'int32' | 'uint32' | 'int64' | 'uint64' | fixdt(1,16,0) | '<data type expression>'

Default: 'Inherit: Inherit via internal rule'

Tips

The block supports HDL code generation using HDL Coder™. HDL Coder supports additional configuration options that affect HDL implementation and synthesized logic. For more information, see HDL Block Properties.

Algorithms

Lump Latency for Divide Block

HDL Coder uses the LumpLatency MATLAB Function to compute the latency of the division operation. The block has four latency modes: Min, Max, Custom, and Zero. For more information, see LatencyStrategy and CustomLatency.

Latency Strategy	Latency Value
Max	The software calculates latency L by using this equation: L = N + 4, where, N is number of iterations. The software determines the value of N by using the fixed-point input and output data type.
Min	The software calculates the latency L by using this equation: L = 2 + ceil( N / 3), where, N is number of iterations. The software determines the value of N by using the fixed-point input and output data type.
Custom	Specify the latency value for the block by entering the value between zero and maximum latency in the Custom latency parameter.
Zero	The latency of the block is 0.

The software calculates the value of N using the signedness, word length and fractional length of the fixed-point input and output. To calculate N, the block follows these steps:

1. Check whether the output data type is a custom type. To determine whether the output data type is a custom type, these conditions must be true:

   • The value of max(DividendWL, DivisorWL) is not equal to OutputWL, where DividendWL is a dividend input word length, DivisorWL is a divisor input word length, and OutputWL is an output word length.

   • OutputFL is not equal to DividendFL -DivisorFL, where DividendFL is a dividend input fractional length, DivisorFL is a divisor input fractional length, and OutputFL is an output fractional length.

   • The value of the logical operation or(isOutputSignedXorInputSigned,isSignednessEqual) is 0. This logical expression gives the value of isOutputSignedXorInputSigned:

     isOutputSignedXorInputSigned = isOutputSigned and isXorInputSignedness

     where isOutputSigned evaluates to 1 when the output is signed and isXorInputSignedness evaluates 1 when the dividend and divisor inputs have different signedness.

     This logical expression gives the value of isSignednessEqual:

     isSignednessEqual = isInputSignednessEqual and isInputOutputSignEqual

     where isInputSignednessEqual evaluates to 1 when both inputs have the same signedness and isInputOutputSignEqual evaluates to 1 when the dividend data input and output have the same signedness.

2. Calculate the number of iterations based on custom output data type.

   • When the output data type is a custom type, this equation defines the iteration number N:

     N = max(DividendWL,DivisorWL) + abs(FractionDiff) + 1,

     where FractionDiff is a fractional difference given by this equation:

     FractionDiff = DividendFL - DivisorFL - OutputFL.

   • When the output data type is not a custom type, N is equal to the output word length.

3. Check the signedness of the divisor and dividend inputs. When the divisor and dividend inputs have different signedness, the software adds one more iteration to the number it calculates using step 2.

To view the LumpLatency block, click the ⇩ icon on the block.

Version History

Introduced in R2020b