Single Port RAM System

Single-port RAM that supports sequential read and write operations

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  • Single Port RAM System block

Libraries:
HDL Coder / HDL RAMs

Alternative Configurations of Single Port RAM System Block:
Simple Dual Port RAM System | Dual Port RAM System | Simple Tri Port RAM System | True Dual Port RAM System

Description

The Single Port RAM System block models a single-port RAM that supports sequential read and write operations. To configure this block, open the block and set the Type of RAM parameter to Single port. By using this block, you can:

  • Create parallel RAM banks by using vector data at the din, addr, and we ports.

  • Specify an initial value for the RAM using the Initial output of RAM parameter.

  • Perform asynchronous read in target hardware by selecting the Use asynchronous read feature in target hardware parameter.

  • Perform cycle-accurate read operation by selecting the Model RAM with one cycle of delay parameter.

  • Use the column-write method to write to specified bits in an addressed memory location.

Examples

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Open Script

This example shows how to use the column-write method to specify the writable portions of bits in an address location for Single Port RAM System block. You can then generate HDL code for the model.

Simulate Model

Load and open the column_write_sram model. The DUT subsystem contains Single Port RAM System block, the data type of the din and we ports determines the writable portion of bits in an addressed memory location.

load_system("column_write_sram");
open_system("column_write_sram/DUT");

The value at the din port is an integer with a value of 980, the value at the addr port is an integer with a value of 25, and the value at the we port is an integer with a value of 6. The binary representation of the we port value indicates that the block selects the third and second columns for writing data in the addressed memory location in the RAM. When you simulate the model, the value at the output dout port is 976. To change these values according to your requirements, see Using the Column-Write Method to Selectively Write to Columns.

sim('column_write_sram.slx');
open_system("column_write_sram");

Generate HDL code

Use HDL Coder™ to generate the HDL code for the model. To generate HDL code for DUT subsystem, run this makehdl command:

makehdl("column_write_sram/DUT");

### Working on the model <a href="matlab:open_system('column_write_sram')">column_write_sram</a>
### Generating HDL for <a href="matlab:open_system('column_write_sram/DUT')">column_write_sram/DUT</a>
### Using the config set for model <a href="matlab:configset.showParameterGroup('column_write_sram', { 'HDL Code Generation' } )">column_write_sram</a> for HDL code generation parameters.
### Running HDL checks on the model 'column_write_sram'.
### Begin compilation of the model 'column_write_sram'...
### Working on the model 'column_write_sram'...
### Working on... <a href="matlab:configset.internal.open('column_write_sram', 'GenerateModel')">GenerateModel</a>
### Begin model generation 'gm_column_write_sram'...
### Copying DUT to the generated model....
### Model generation complete.
### Generated model saved at <a href="matlab:open_system('hdlsrc/column_write_sram/gm_column_write_sram.slx')">hdlsrc/column_write_sram/gm_column_write_sram.slx</a>
### Begin VHDL Code Generation for 'column_write_sram'.
### Working on column_write_sram/DUT/SinglePortRAM_generic as hdlsrc/column_write_sram/SinglePortRAM_generic.vhd.
### Working on column_write_sram/DUT as hdlsrc/column_write_sram/DUT.vhd.
### Code Generation for 'column_write_sram' completed.
### Generating HTML files for code generation report at <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc25a_2864802_2630442/tp4452170f/hdlcoder-ex10710190/hdlsrc/column_write_sram/html/index.html')">index.html</a>
### Creating HDL Code Generation Check Report file:///tmp/Bdoc25a_2864802_2630442/tp4452170f/hdlcoder-ex10710190/hdlsrc/column_write_sram/DUT_report.html
### HDL check for 'column_write_sram' complete with 0 errors, 1 warnings, and 0 messages.
### HDL code generation complete.

Limitations

  • When you build the FPGA bitstream for the RAM, the global reset logic does not reset the RAM contents. To reset the RAM, implement the reset logic.

  • The RAM address can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long.

Ports

Input

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Data to write, specified as a scalar or a vector. You can write the data into the RAM memory location when the write enable signal at port we is true. This value can be an integer, or of type double, single or half. The value can also be a fi object and can be real or complex.

Bus Support:

You can use non-virtual bus and arrays of buses for HDL code generation.

Data Types: single | double | half | int8 | int16 | uint8 | uint16 | Boolean | fixed point

Address to write or read, specified as a scalar or a vector. Use this address to write data to RAM when the signal at port we is true. The block reads the value from the specified memory location when the signal at port we is false. This value can be either a fixed-point (fi) or an unsigned integer and must be between 2 and 31 bits long.

Data Types: uint8 | uint16 | fixed point

Write enable, specified as a scalar or a vector. When the signal at the port we is true, the block writes the data into the specified memory location. When the signal at the port we is false, the block reads the value from the memory location specified by the addr port.

Note

To use column-write method, the data type must be an integer or a fixed-point.

Data Types: uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

Output

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Output data, returned as a scalar or a vector. The RAM reads data from the memory location specified by the addr port when the signal at port we is false.

Parameters

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Main

Type of RAM, specified as either:

  • Single port — Create a single port RAM with write data, address, and write enable data as inputs and read data as the output.

  • Simple dual port — Create a simple dual port RAM with write data, write address, write enable, and read address as inputs, and data from the read address as the output.

  • Dual port — Create a dual port RAM with write data, write address, write enable, and read address as inputs, and data from the read address and write address as the outputs.

  • True dual port — Create a true dual port RAM with write data a and b, write and read addresses for a and b, and write enable a and b as inputs and data from write addresses a and b as the outputs.

  • Simple tri port — Create a simple tri port RAM with write data, write address, write enable, and read addresses a and b as inputs and data from read addresses a and b as the outputs.

The code generator dynamically configures the input and output ports of the block based on the RAM type that you specify.

Programmatic Use

Block Parameter: RAMType
Type: character vector, string
Values: Dual port | Simple dual port | Single port | True dual port | Simple tri port
Default: Single port

Enable this option to allow the hardware to execute a read instruction immediately, without waiting one cycle.

Programmatic Use

Block Parameter: AsyncRead
Type: character vector, string
Values: 'on' | 'off'
Default: 'off'

Select the behavior for write output as New data or Old data:

  • New data — Send out new data at the address to the output.

  • Old data — Send out old data at the address to the output.

Dependencies

To enable this parameter, clear the Use asynchronous read feature in target hardware parameter.

Programmatic Use

Block Parameter: WriteOutputValue
Type: character vector, string
Values: New data | Old data
Default: New data

Specify the initial simulation output of the RAM by using one of these options:

  • A scalar value.

  • A vector with a one-to-one mapping between the initial value and the RAM words.

  • An n-by-m matrix with a one-to-one mapping between the initial values and the RAM words in the RAM banks, where n represents the number of RAM banks and m represents the number of address locations in the RAM block, or vice-versa.

Programmatic Use

Block Parameter: RAMInitialValue
Type: integer, floating point
Values: 0.0 | Scalar | Vector
Default: 0.0

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

Advanced

Since R2024b

  • When you select this parameter, the RAM delays the input data by one cycle before the output can read it. Use this option to ensure the block is cycle-accurate with the generated HDL code.

  • When you clear this parameter, the RAM reads and outputs the input data immediately, but adds one cycle of latency during HDL code generation. Use this option to leverage clock-rate pipelining when you specify an oversampling value or work with multirate models.

Dependencies

To enable this parameter, clear the Use asynchronous read feature in target hardware parameter.

Programmatic Use

Block Parameter: ModelRAMDelay
Type: character vector, string
Values: 'on' | 'off'
Default: 'on'

Since R2025a

  • When you set this parameter to serial, the code generator infers parallel banks of RAM from vector inputs to RAM System block.

  • When you set this parameter to parallel:

    • The code generator does not scale up RAM consumption with the size of the vector input when you generate HDL Code. Instead, it applies each operation of the input signals one at a time, starting with the first index. Enabling serial access allows you to leverage multicycle RAM access at a faster clock rate while modeling with a vector input at the data rate.

    • If the RAM System block exists in a clock-rate pipelining region, the serialization uses a clock-rate implementation instead of local multirate implementation.

Dependencies

To enable this parameter, clear the Model RAM with one cycle of delay parameter or enable the Use asynchronous read feature in target hardware parameter.

Programmatic Use

Block Parameter: VectorAccess
Type: character vector, string
Values: 'serial' | 'parallel'
Default: 'serial'

Alternative Configurations

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The Simple Dual Port RAM System block models RAM that supports simultaneous read and write operations through a single output port for read data. To configure this block, open the block and set the Type of RAM parameter to Simple dual port.

Libraries:
HDL Coder / HDL RAMs

The Dual Port RAM System block models RAM that supports simultaneous read and write operations through output ports for read data and write data. This blocks allows concurrent access to different memory addresses. To configure this block, open the block and set the Type of RAM parameter to Dual port.

Libraries:
HDL Coder / HDL RAMs

Since R2023b

The Simple Tri Port RAM System block models RAM that supports simultaneous read and write operations through two output ports for read data. This blocks allows concurrent access to different memory addresses. To configure this block, open the block and set the Type of RAM parameter to Simple tri port.

Libraries:
HDL Coder / HDL RAMs

Since R2023b

The True Dual Port RAM System block models RAM that supports simultaneous read and write operations through two output ports for read data. This blocks allows concurrent access to different memory addresses for both read and write operations. To configure this block, open the block and set the Type of RAM parameter to True dual port.

Libraries:
HDL Coder / HDL RAMs

More About

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Extended Capabilities

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C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2017b

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See Also

Objects

Blocks

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