Choose an Interface for an IP Core

You can generate an IP core for a design under test (DUT) and interface the generated IP core to the rest of your system by using AXI4, AXI4-Lite, AXI4 Master, AXI4-stream, AXI4-Stream Video, internal or external I/O, or FPGA data capture interfaces. The image shows how the interfaces connect the processor to the DUT:

To determine the most appropriate interface, consider the intended use, supported data types, required tools, and the associated strengths and limitations of each interface.

Supported Interface Methods

This table summarizes the key aspects of the different available interfaces, target use cases, supported data types, and interface limitations.

Interface Type	Use Cases	Data Types	Strengths	Limitations
Register Interface (AXI4-Lite/AXI4)	Use this interface to access the control and status registers in your design. You can choose between AXI4-Lite or AXI4 protocol for the register interface. Use AXI4-Lite if you need only lightweight data transfers. Use AXI4 to connect to components that support burst data transfers.	Supported data types: Scalar Vector (Since R2017a) Bus (Since R2021a) Double (Since R2023a) Single (Since R2017a) Half (Since R2022a) Fixed-point (> 32-bit fixed point supported since R2023a) Complex (Since R2024a) Bit widths greater than 128 bits (Since R2024b) Unsupported data types: Matrix Enumeration Array of buses	AXI4-Lite Simplified protocol for easy implementation. Ideal for low throughput control registers. Lower hardware complexity. AXI4 High-performance, high-bandwidth transfers with burst transfer support. Flexible protocol that allows for allowing multiple outstanding addresses and out-of-order transaction completion	The register interface does not support simultaneous read and write transactions. You cannot map some DUT ports to AXI4-Lite interfaces and other DUT ports to AXI4 interfaces for the same design.
AXI4 Master	Use this interface for designs that require you to access memory, or to control other IP cores with AXI4 or AXI4-Lite interfaces. Example applications include moving large amounts of data between your algorithm and external DDR memory.	Supported data types: Scalar Vector (Since R2020a) Fixed-point Single Double Bit widths greater than 128-bits (Since R2024b) Unsupported data types: Complex Enumeration Matrix Bus Array of buses Double Half	Full support of AXI4 features, which allows for efficient, high-speed communication. Allows for control over data transfers by allowing for the initiation of read and write transactions. Bidirectional transfer of data.	When you use the AXI4 Master interface, you must: Set the synthesis tool to Xilinx® Vivado® or Intel® Quartus®. Microchip Libero® SoC is not supported. Set the Processor/FPGA synchronization parameter in task 1.3 Set Target Interface of the HDL Workflow Advisor to Free Running. Keep the total bit width of the concatenated non-scalar data at less than or equal to 1024.
AXI4-Stream	Use this interface for moving streaming data or transferring data at high speeds. Example applications include: Connecting to analog/digital converters (ADCs/DACs). Connecting to video pipelines. Transferring large amounts of data between processors and FPGAs using direct memory access (DMA). You can model your algorithm to operate on a stream of samples or on frames.	Supported data types: Single (Since R2022a) Half (Since R2022a) Fixed-point Complex (Since R2021b) Double Supported for sample-based modeling: Scalar Vector Since R2021a Supported for frame-based modeling: Vector Since R2022b Matrix Since R2022b Unsupported data types: Enumeration Bus Array of bus 3-D matrices	Optimized for high-speed, continuous-data streams. Minimal protocol overhead and support for flexible data widths. Allows you to stream and transfer large amounts of data.	When using the AXI4-Stream interface, you must: Set the synthesis tool to Xilinx Vivado or Intel Quartus. Microchip Libero SoC is not supported. Set the Processor/FPGA synchronization parameter in task 1.3 Set Target Interface of the HDL Workflow Advisor to Free Running.
AXI4-Stream Video	Use this interface for video streaming applications. You can model the algorithm to operate on a stream of samples or on frames.	Supported data types: Fixed-point For frame-based modeling, matrices are supported.(Since R2023a). Unsupported data types: Scalar 3-D matrices Complex Enumeration Bus Array of bus Vector Bit widths greater than 128 bits	Tailored for video applications, and supports common video resolutions and color formats. Incorporates frame synchronization and timing information, which simplifies video processing pipeline integration.	When using the AXI4-Stream Video interface, you must: Set the synthesis tool to Xilinx Vivado or Intel Quartus. Microchip Libero SoC is not supported. Set the Processor/FPGA synchronization parameter in task 1.3 Set Target Interface of the HDL Workflow Advisor to Free Running. When you choose your algorithm to operate on frames, you cannot use the MATLAB-to-HDL workflow.
Internal I/O	Use this interface to connect directly to other IP cores in the reference design.	Supported data types: Scalar Vector (Since R2020b) Fixed-point Bit widths greater than 128 bits (Since R2024b) Unsupported data types: Complex Enumeration Bus Array of bus Matrix Half Single Double	Modeling is less complex and the code generator does not generate additional protocol logic.	You can map internal I/O interfaces only when you define these interfaces in your reference design. Non-scalar data is bit-concatenated together. The total bit width of the concatenated data must be less than or equal to 65536.
External I/O and External Port	Use this interface to connect to peripherals on your hardware board, such as LEDs, push buttons, DIP switches, FPGA pins, and so on.	Supported data types: Scalar Vector (Since R2021a) Fixed-point Bit widths greater than 128 bits (Since R2024b) Unsupported data types: Complex Enumeration Bus Array of bus Matrix Half Single Double	Modeling is less complex and the code generator does not generate additional protocol logic. Allows for direct mapping to physical I/O pins and simplifies external hardware integration.	Reduced flexibility in terms of design reusability and portability across different hardware platforms. Non-scalar data is bit-concatenated together. The total bit width of the concatenated data must be less than or equal to 65535.
FPGA Data Capture	Use this interface to capture raw data from outputs or signals by using test points in your design and then use the data to debug your design.	Supported data types: Scalar Fixed-point Unsupported data types: Complex Enumeration Bus Array of bus Matrix Vector	Allows for real-time debugging, which enables you to quickly identify design issues. Enables you to debug your IP core while it is running on hardware by using conditional logic triggers to perform event-based capture. Enables you to observe raw signal data at the FPGA level without the need for interface protocol modeling.	Consumes FPGA resources, which can potentially limit the available resources for other aspects of the FPGA design. You must establish a JTAG connection to your board to connect to the data capture IP. You must have an HDL Verifier™ license to use this interface.

Register Interface (AXI4-Lite/AXI4)

Use this interface to access control and status registers in your design. You can choose between the AXI4-Lite or AXI4 protocols. Use AXI4-Lite if you need only lightweight data transfers. Use AXI4 to connect to components that support burst data transfers.

Interface Name	Considerations
AXI4-Lite	Limited bandwidth. Not suitable for high-throughput data transfers.
AXI4	Higher hardware resource consumption.

For additional information, see:

• Model Design for AXI4 Slave Interface Generation

• Map Bus Data Types to AXI4 Slave Interface

AXI4 Master

Use the AXI4 Master interface for designs that require you to access memory or control other IP cores with AXI4 or AXI4-Lite interfaces. For example, you can use this interface to move large amounts of data between your algorithm and external DDR memory.

Interface Name	Considerations
AXI4 Master	This interface has a more complex implementation and requires more resources compared to the AXI4-Stream interface.

For more information, see:

• Model Design for AXI4 Master Interface Generation

• Generate IP Core with AXI4 Master Interface to Access External Memory

AXI4-Stream and AXI4-Stream Video

Use the AXI4-Stream interface to move streaming data or transfer data at high speeds. Example applications include:

• Connecting to analog/digital converters (ADCs/DACs)

• Connecting to video pipelines

• Transferring large amounts of data between processors and FPGA by using DMA

You can model the algorithm to operate on a stream of samples or on frames. You can model your algorithm to operate on a stream of samples or on frames.

For example, this image shows how you can use an AXI4-Stream interface between multiple IP cores.

Interface Name	Considerations
AXI4-Stream	Lacks native support for addressing, which means this interface requires additional logic for data routing. Not suitable for memory-mapped access patterns. When not using the frame-to-sample optimization, non-scalar data is bit-concatenated together according to the setting of Packing Mode parameter in the HDL Coder Workflow Advisor Task 1.2. Set Target Interface > Interface Options. The total bit width of the concatenated data must be less than or equal to 1024.
AXI4-Stream Video	Limited use cases for non-video applications. Requires understanding of video processing concepts. This interface may have additional overhead compared to a generic AXI-Stream interface, and currently supports only AMD®.

For additional information, see:

• Model Design for AXI4-Stream Interface Generation

• Generate IP Core with AXI-Stream Interface

• Generate IP Core for Frame-Based Model with AXI4 Stream Interfaces

• Generate IP Core with AXI4-Stream Video Interface

• Generate IP Core from Frame-Based Model with AXI4 Stream Video Interface

Internal I/O

Use the internal I/O interface to connect directly to other IP cores in the reference design. The internal I/O interface is defined by the reference design. When you map to an internal I/O interface, HDL Coder™ connects the other IP cores with a wire.

Interface Name	Challenges
Internal I/O	Since there is no established protocol you have to consider additional factors such as supported port widths, synthesis tool specific naming formats, and so on, when integrating multiple components together.

For additional information, see addInternalIOInterface.

External I/O and External Port

Use this interface to connect to peripherals on your hardware board, such as LEDs, push buttons, DIP switches, FPGA pins, and so on.

Interface Name

Considerations

External I/O

You must consider the hardware details and effects of the peripherals you are connecting to. This interface has reduced flexibility in terms of design reusability and portability across different hardware platforms. External I/O interfaces are defined by the board author, and typically use the name of the peripherals. For example, for a board with an array of eight LEDs, you map to the interface LEDs General Purpose [0:7]. You can also map to arbitrary pins on your FPGA or peripherals that are not made available through predefined external I/O interfaces. In this case, map to the external port interface and specify the desired FPGA pins for mapping. When using the generic IP core workflow, map the external port interface to expose DUT ports directly on the IP core boundary.

For additional information, see:

• Define Custom Board and Reference Design for AMD Workflow

• Define Custom Board and Reference Design for Intel Workflow

• Define Custom Board and Reference Design for Microchip Workflow

FPGA Data Capture

To interface with internal signals in your IP core, use an FPGA data capture. When you develop a model using Simulink^®, you can automatically integrate this method with the IP core. This method usually involves establishing a JTAG connection to the host. You can employ test points to monitor the internal signals of the IP core while your hardware-software design runs on the hardware. FPGA data capture is useful when debugging and analyzing the design of the IP core because it eliminates the need for interface protocol modeling.

You can use FPGA data capture in the Run and Verify IP Core on Target Hardware stage of the hardware-software co-design process.

Interface Name

Consideration

FPGA Data Capture

You must integrate the FPGA data capture IP into the design. The data capture IP can be automatically integrated into the design if you use Simulink. If you are not using Simulink, you must manually integrate the data capture IP. This interface requires that you understand the internal workings of the FPGA design, including the signal functionality and expected behavior. When mapping to the FPGA data capture interface, the data capture IP is automatically integrated into the design, which consumes additional FPGA resources.

For additional information, see Debug IP Core Using FPGA Data Capture.

Related Topics

• Choose a Method to Interact with IP Cores on Target Hardware