Generate an FPGA-in-the-loop (FIL) block or System object from existing HDL files
FPGA-in-the-loop (FIL) enables you to run a Simulink® or MATLAB® simulation that is synchronized with an HDL design running on an Xilinx®, Microchip, or Altera® FPGA board.
This link between the simulator and the board enables you to:
Verify HDL implementations directly against algorithms in Simulink or MATLAB.
Apply data and test scenarios from Simulink or MATLAB to the HDL design on the FPGA.
Integrate existing HDL code with models under development in Simulink or MATLAB.
Open the FPGA-in-the-Loop Wizard App
Simulink Toolstrip: In the Apps tab, under Verification, Validation and Test, click the HDL Verifier icon. Select HDL Cosimulation on the left pane, and click Import HDL Files.
MATLAB command prompt: Enter
filWizard. You provide the HDL code and all related information for creating a FIL block for simulation with an FPGA device.
filWizard( relaunches the
FIL Wizard using a configuration file from a previous session. At the end of
each FIL Wizard session, the tool saves a MAT-file that contains the session
information. You can use this MAT-file to restore the session later.
Introduced in R2012b