Creating an FPGA-in-the-loop link between the simulator and the board enables you to:
Verify HDL implementations directly against algorithms in Simulink® or MATLAB®.
Apply data and test scenarios from Simulink or MATLAB to the HDL design on the FPGA.
Integrate existing HDL code with models under development in Simulink or MATLAB.
Before you can use FPGA-in-the-loop (FIL) simulation, you must download the support package for your board. See Download FPGA Board Support Package. Alternatively, you can manually create custom board definition files for use with FIL simulation. See FPGA Board Customization.
|Generate HDL verification artifacts and follow verification workflows from a Simulink subsystem (Since R2020b)
|Generate an FPGA-in-the-loop (FIL) block or System object from existing HDL files
|Visualize, measure, and analyze transitions and states over time
|FIL simulation with MATLAB
|Simulate HDL code on FPGA hardware from Simulink
- FPGA-in-the-Loop Simulation Workflows
Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.
- FPGA-in-the-Loop Simulation
FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.
FIL Requirements and Preparation
- Prepare DUT For FIL Interface Generation
DUT guidelines for FIL simulation of blocks and System objects.
- Download FPGA Board Support Package
The FPGA board support packages contain the definition files for all the supported boards for FPGA-in-the-loop (FIL) simulation, FPGA data capture, or AXI manager.
- Set Up FPGA Design Software Tools
Set the MATLAB path to Xilinx®, Microchip, and Intel® software.
- Guided Hardware Setup
Describes the steps in the automated support package setup process for configuring hardware for use with FPGA-in-the-loop, AXI manager, or FPGA data capture.
- Manual Hardware Setup
Describes the steps necessary to prep hardware and hardware tools for FIL.
- Configure Logic Analyzer
Adjust settings in the Logic Analyzer.
Generate FIL Interface from Legacy Code
- Block Generation with the FIL Wizard
Generate a FPGA-in-the-Loop block from existing HDL source files, then include the FPGA implementation in a Simulink simulation.
- System Object Generation with the FIL Wizard
Generate a FPGA-in-the-Loop System object from existing HDL source files, then include the FPGA implementation in a MATLAB simulation.
- Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop
This example shows you how to set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™.
- Verify Digital Up-Converter Using FPGA-in-the-Loop
This example shows you how to verify a digital up-converter design generated with Filter Design HDL Coder™ using FPGA-in-the-Loop simulation.
Generate FIL System Object from MATLAB Code (requires HDL Coder license)
- FIL Simulation with HDL Workflow Advisor for MATLAB
Generate an FPGA-in-the-loop System object and test bench using HDL Workflow Advisor.
Generate FIL Block from Simulink Model (requires HDL Coder license)
- Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.
- FIL Simulation with HDL Workflow Advisor for Simulink
Generate an FPGA-in-the-loop model using HDL Workflow Advisor.
Fixes for common error messages and issues.