ADC Tutorial

This tutorial example shows you how to design a second order Delta Sigma Analog to Digital Converter in Simulink®. The example starts with a simple system-level design of a first-order delta sigma ADC and progressively refine its design.

Architecture

The ADC system consists of three components:

• the analog anti-aliasing filter,

• the delta sigma ($\Sigma \Delta )$ converter,

• the digital multi-rate multi-stage decimation filter.

A system-level block diagram of an ADC is shown below, in Figure 1.

The analog filter constraints the bandwidth of the input signal, so that when it is sampled at a fixed rate, eventual higher frequency components are eliminated and do not cause aliasing.

The sigma-delta converter operates at a high sampling rate, and generates an oversampled digital representation of the Analog data. The output is a two-level signal that toggles with a frequency that is proportional to the amplitude of the input signal.

The digital filter reduces the data rate of the discretized signal by applying decimation. It creates a higher resolution but lower sample rate digital output which represents the desired signal.

Contents

The example walks you through the design process in three steps:

• System-Level Model of DSM ADC — Design a system-level model of DSM ADC.

• SystemVerilog Module Generation — Generate SystemVerilog module, cosimulate the Simulink® testbench and the filter implementation with Cadence Incisive®.

• Final System-Level Model — Put together the final system-level model of the ADC.