This example shows the steady-state and transient performance of a 12-pulse, 1000 MW (500 kV-2kA) 50/60 Hz HVDC transmission system.
Silvano Casoria (Hydro-Quebec)
When modeling line-commutated converter based HVDC systems you can use two types of model, depending on the range of frequencies to be represented:
The detailed model such as the one presented in the power_hvdc12pulse model includes detailed representation of the converter unit with its power electronic thyristor bridge and converter transformer. This model is well suited for observing harmonics and control system dynamic and transient performance.
The average model such as the one presented here where the converter unit (bridge and transformer) is represented by an equivalent voltage source generating the bridge average DC voltage and AC sources generating the fundamental component of the currents flowing into the network. This model does not represent harmonics, but the dynamics resulting from control system and power system interaction is preserved. This model allows using a time step that is higher than the one of the control system or the network. Optimal performance however is obtained by using the same time step of the control system regulators.
A 1000 MW (500 kV, 2kA) DC interconnection is used to transmit power from a 500 kV, 5000 MVA, 60 Hz network to a 345 kV, 10 000 MVA, 50 Hz network. The rectifier and the inverter are average models of 12-pulse converters representing two 6-pulse thyristor bridges connected in series. The rectifier and the inverter are interconnected through a 300 km distributed parameter line and two 0.5 H smoothing reactors.
The converter transformer linear representation is part of the average model block. The transformer tap changers are not simulated and fixed taps are assumed as model inputs. At the rectifier the tap ratio (Nprimary/Nsecondary) is 0.9 (pu) and at the inverter it is 0.96 (pu). Reactive power required by the converters is provided by a set of capacitor banks plus 11th, 13th and high pass filters for a total of 600 Mvar on each side. Note that since no harmonics are generated by the average converter model the Mvar could be provided entirely by capacitor banks.
Two circuit breakers are used to apply faults on the inverter AC side and rectifier DC side. Note that since thyristor valves are not present the 12-pulse Firing Control block is no longer necessary in the average model.
DC Protection functions are implemented in each converter. At the rectifier, the DC fault protection will detect and force the delay angle into the inverter region so to extinguish the fault current. At the inverter, the commutation failure prevention control will detect AC faults and reduce the maximum delay angle limit in order to decrease the risk of commutation failure. Note that the commutation failure phenomenon is not possible in the average model.
To assist the user in identifying conditions that may produce this phenomenon an indication from the model is provided ( CF_alarm signal available from the Bus Selector block of the rectifier and inverter models). The Low AC Voltage Detection blocks will lock the DC fault protection when a drop in the AC voltage is detected. The Master Control block initiates the starting and stopping of the converters as well as the ramping up and down of the current references.
A description of the control systems is provided in the HVDC Transmission System Case Study of the User's Manual. The firing angle order (alpha_ord) output of the controller is an input of the average model.
The power system and the control system are both discretized for a sample time Ts=50 us. The "Model initialization" section of the model automatically sets Ts = 50e-6 in your MATLAB® workspace. It also sets the average model time step Ts_avg equal to Ts.
The system is programmed to start and reach a steady state. Then steps are applied on the reference current of the rectifier and on the inverter reference voltage in order to observe the dynamic response of the regulators. Finally, a stop sequence is initiated to bring the DC power down before blocking the converters.
Start the simulation, open the RECTIFIER and INVERTER scopes (in the Data Acquisition subsystem) and observe the DC line voltage on trace 1 (1pu = 500 kV) and the DC line current (reference and measured values) on trace 2 (1pu = 2 kA).
Start-up and Stop
In the Master Control, the converters are unblocked and started by ramping the rectifier and inverter reference current.
At t = 0.02 s (i.e. when the converters at unblocked), the reference current is ramped to reach the minimum value of 0.1 pu in 0.3 s (0.33 pu/s). At the end of this first ramp (t = 0.32 s) the DC line is charged at its nominal voltage and DC voltage reaches steady-state.
At t= 0.4 s, the reference current is ramped from 0.1 pu to 1 pu (2kA) in 0.18 s (5 pu/s). At the end of this starting sequence (t=0.58 s), the DC current reaches steady state. The RECTIFIER then controls the current and the INVERTER controls the voltage.
In steady-state, the alpha firing angles (trace 3) are 17.7 degrees and 144.5 degrees respectively on the RECTIFIER and INVERTER sides. Note that in the detailed model these traces (16.5 degrees for the rectifier and 143 degrees for the inverter) are not the measured firing delay angles but the corresponding orders from the control regulators. In the detailed model, the firing angles are smaller because the regulators must advance the firing orders by two time steps in order to compensate for the delays introduced by interfacing of input AC voltages and output firing pulses of the 12-pulse Firing Control block. The extinction angle gamma value is an output of the average model. It is used at the INVERTER and shown in trace 5. In steady-state, its value is 23 degrees.
The control mode of operation (an integer between 0 to 6) is shown in trace 4 (0= blocked; 1=Current control; 2=Voltage control; 3=Alpha minimum limitation; 4=Alpha maximum limitation; 5=Forced or constant alpha; 6=Gamma control).
At t = 1.4 s the Stop sequence is initiated by ramping down the current to 0.1 pu.
At t = 1.6 s a Forced-alpha at the Rectifier extinguishes the current and at the Inverter the Forced-alpha brings down the DC voltage.
At t = 1.7 s the pulses are blocked in both converters.
Step response of current and voltage regulators
Verify in the Master Control that the "Enable Ref. Current Step" switch is in the upper position. This switch is used to apply a step on the reference voltage. Also verify that the Ref. Voltage Step is enabled in the Inverter Control. Start the simulation.
At t=0.7 s, a -0.2 pu step is first applied on the reference current (decrease from 1 pu to 0.8 pu ) and at t=0.8 s, the reference current is reset to its 1 pu original value. The current stabilizes in approximately 0.1 seconds. Steps are also applied on the reference voltage of the inverter (-0.1 pu / +0.1 pu at t=1.0 s / 1.1s).
DC line fault at the rectifier
Deactivate the steps applied on the current reference and on the voltage reference in the Master Control and in the inverter control respectively by setting the switches in lower position.
The DC Fault protection (DCPROT) in the rectifier is activated by default. In the DC Fault block, change to 1 the 100 multiplication factor in the Switching times so that a fault is now applied at t = 0.7 s.
Reduce the Simulation stop time from 2 to 1.4 s. Open the FAULT scope to observe the DC fault current. Restart the simulation.
At fault application the DC current quickly increases to 2.63 pu and the DC voltage falls to zero at the rectifier. This DC voltages drop is seen by the Voltage Dependent Current Order Limiter (VDCOL) which reduces the reference current to 0.3 pu at the rectifier. A DC current still continues to circulate in the fault.
At t = 0.77 s, the rectifier alpha firing angle is forced to 166 degrees by the DC protection because a DC voltage drop is detected (VdL< 0.5 pu for more than 70 ms). The rectifier now operates in inverter mode. The DC line voltage becomes negative and the energy stored in the line is returned to the AC network, causing rapid extinction of the fault current at its next zero-crossing.
Alpha is released at t = 0.82 s and the normal DC voltage and current recover in approximately 0.4 s.
AC line-to-ground fault at the inverter
In the DC Fault block, change the multiplication factor of 1 in the Switching times to 100, so that the DC fault is now disabled. In the A-G Fault block, change to 1 the 100 multiplication factor in the Switching times so that a 6 cycles line-to-ground fault is now applied at t = 0.7 s.
The Low AC voltage detection (LACVD) subsystem in the rectifier and inverter protections and the Commutation Failure Prevention Control (CFPREV) in the inverter protection are activated by default.
Restart the simulation.
Note that the 120 Hz oscillations in the DC voltage and currents which are normally observed during single-phase fault with a detailed model do not exist in the average model. Indeed, only positive-sequence fundamental components of AC quantities are significant in the average model. The VDCOL would not operate during the fault. The system recovers in approximately 0.2 s after fault clearing (see the measured DC power Pd).
Abnormal inverter operation resulting from a commutation failure malfunction (CF) due to AC faults are not correctly represented by the average model equations. To assist the user in identifying such a condition an alarm signal (CF_alarm) is set whenever the onset of a CF is predicted.
Look at the CF_alarm signal at the inverter, triggered at t = 0.73 s. Open the CF_alarm block (inside the HVDC_CONV_AVG block of the inverter model) to examine the logic.
Look at the A_min_I signal of the PROTECTION INVERTER scope. This signal monitors the Commutation Failure Prevention (CFPREV) output of the Inverter Protection block. The A_min signal is used to decrease the delay angle limit in order to increase the commutation margin during and after the fault.
Finally, deactivate the CFPREV protection by deselecting the "ON State" in the CFPREV dialog box. Restart the simulation and observe the difference in recovery time of the DC transmission.