Parallel Link Design
The Parallel Link Designer app provides a dedicated system-level design and analysis environment for parallel links. Capture your parallel link designs graphically and experiment with different physical layouts and parameter sweeping to determine setup/hold timing and voltage margins for high-speed parallel links. Analyze parallel interfaces for compliance with timing and signal integrity constraints.
Use the Parallel Link Designer app to configure parallel links. Set simulation parameters, specify corner conditions, and define stimulus patterns. Set up pre-layout analysis to run SPICE and to conduct waveform and timing data analysis to analyze your custom parallel links. View and interpret the results using the Signal Integrity Viewer app. You can also set up and analyze the post-layout PCB database of your parallel link design if you have a license for RF PCB Toolbox™. You can modify the stackup and padstack models and customize vias and see how the changes impact your design.
Parallel Link Design Basics
- Clock Modes
Learn about different clock modes in AMI models.
- PAMn Capabilities
Design and simulate systems and test AMI models using PAMn signaling.
- Elements In Link Designer Apps
List of elements used by the Serial Link Designer and Parallel Link Designer apps.
- List of Operations Available in Signal Integrity Viewer
Refresh, zoom, use markers and thresholds, and modify display in Signal Integrity Viewer app.
- Run Parallel Simulations in Signal Integrity Toolbox
Reduce the time required to run a complete set of simulations by running the simulations in parallel with Parallel Computing Toolbox™.
Configure Parallel Link Projects
- Simulation Parameters Used in Parallel Link Design
Set parameters to control SPICE simulation and statistical, time domain, and waveform analysis.
- Specify Corner Conditions in Parallel Link Design
Specify process corners and etch corners to simulate in parallel link project.
- Stimulus Patterns in Parallel Link Design
Define stimulus patterns for time domain analysis in parallel link project.
- Model Jitter and Noise While Designing Parallel Link
Add TX clock jitter, RX clock jitter, RX clock recovery jitter, and noise.
- Pre-Layout Analysis of Parallel Link
Learn the basics of pre-layout analysis.
- Customize Parallel Link Project for Pre-Layout Analysis
Edit transmission line models, designators, S-parameters, and IBIS files to customize pre-layout analysis.
- Results of Pre-Layout Analysis in Parallel Link
View, interpret, and debug the pre-layout analysis results.
Post-Layout Verification (Requires RF PCB Toolbox)
- Post-Layout Verification of Parallel Link
Verify system-level SI and timing margins of PCB design databases.
- Stackup and Extraction Control in Parallel Link Project
Edit stackups and control padstack models.
- Via and Stackup Management in Parallel Link Project
Manage vias and stackups using Stackup Editor and PadStack Editor.
- Post-Layout to Pre-Layout Extraction
Create topologies from extracted PCB data.
Results to View with Signal Integrity Viewer
- Network Characterization Results
Table of data and waveforms to view in the Network tab after performing network characterization.
- Statistical Analysis Results
Table of data and waveforms to view in the Statistical tab after performing statistical analysis.
- Time Domain Analysis Results
Table of data and waveforms to view in the time domain tab after performing time domain analysis.
- Eye Measurement and Reporting
Measure and report eye diagram metrics.
- Managing Simulation Data and Results
Quickly and efficiently sort through the simulation data and results of the link design project.
- Advanced Visualization Using Signal Integrity Viewer
Plot frequency and time domain waveforms and results against single or multiple variables.