Parallel Link Design

Implement a 1-slot generic DDR5 RDIMM interface for pre-layout analysis or post-layout verification.

Implement a low-power DDR5 (LPDDR5) interface for pre-layout analysis or post-layout verification.

Implement a 32-bit GDDR6 interface for pre-layout analysis or post-layout verification.

Use the Parallel Link Designer app to perform timing analysis for the DDR (Double Data Rate) family of memory interface protocols. You can use either Setup and Hold margins or by waveform eye-diagram compliance masks to perform the timing analysis. The DDR Memory Down (DDR4_MD) example kit uses both timing and waveform mask analysis. Specifically for DDR4 systems, timing analysis is performed on clock-address/command interface, and waveform compliance masks are applied to strobe-data(DQS-DQ) interface. Other DDR types may use only timing analysis, or only waveform mask analysis or a blend depending on individual standards.

Demonstrates the use of Parallel Link Designer in the Signal Integrity Toolbox™ in MATLAB® to set up a post-layout analysis of a DDRx interface on a Main Board having a CPU connected to two DIMM slots to verify that waveform quality and timing margins are met by the PCB database. Many of the steps illustrated in this example are also applicable to Serial Link Designer for post-layout analysis of SERDES links.

Use Signal Integrity Toolbox™ for MATLAB to analyze a DDR5 interface with the IBIS-AMI feature Clock-Forwarding enabled for analysis of system margins. IBIS BIRD 204, "DQ_DQS GetWave Flow for Clock Forwarding Modeling," adds the ability to pass in an external Clock signal (or Strobe, as appropriate) to an Address (or Data) IBIS-AMI receiver GetWave model using the clock_times pointer defined by the IBIS specification. A new AMI Reserver Parameter, Rx_Use_Clock_Input, is used to enable this functionality.