Serial Link Design

Design high speed serial links such as PCIe, USB, and Ethernet

The Serial Link Designer app provides a dedicated system-level design and analysis environment for multi-gigabit serial links. Capture your serial link designs graphically and experiment with different physical layout and equalization strategies to predict how design alternatives affect operating margins and the bit error rate (BER) of the link. Use network characterization to model the behavior of the unequalized analog network. This enables quick evaluation of the analog channel design for different trade-offs. Predict the end-to-end behavior of the link using SerDes equalization techniques and clock recovery models obtained by statistical and time-domain analysis. Determine the effect of aggressor signals on overall BER of the channel using crosstalk analysis.

Use the Serial Link Designer app to configure high speed serial links. Set simulation parameters, specify corner conditions, and define stimulus patterns. Set up pre-layout analysis to run SPICE, network characterization, statistical and time domain simulations to analyze your custom serial links. View and interpret the results using the Signal Integrity Viewer app. You can also set up and analyze the post-layout PCB database of your serial link design if you have a license for RF PCB Toolbox™. You can modify the stackup and padstack models and customize vias and see how the changes impact your design.

Featured Examples

Analyze Backplane with Line Cards

Analyze a serial link consisting of a backplane and two line cards with the Serial Link Designer app. You can model the SerDes drivers/receivers, capture a topology for analysis, run network characterization, and evaluate the impact of different solution space variables on your design's performance.

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Creating Compliance Masks in Serial Link Designer

Create compliance masks and apply them to the simulation results in the Serial Link Designer app. The masks used in the Serial Link Designer app are defined in the rules file. Rules files are text files that define the mask limits for a parameter, or parameters in the channel simulation results. These are user created files that can be applied as eye masks or network loss characteristics. The file extension of a rules file must be “.rules” so that the Serial Link Designer app can recognize it as a mask file. The file must also be located in the <Project_Directory>\si_lib\rules\ directory of the project.

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Channel Operating Margin (COM) for Serial Link

Channel Operating Margin (COM) is a figure of merit for a passive channel expressed in decibels and is calculated using the ratio of signal amplitude factors to noise amplitude factors. Channel bit rate, insertion loss, return loss, cross-coupling, transmitter and receiver equalization and IC package models are some of the factors applied to determine COM. While it is required for compliance in some applications, COM can also be a valuable part of channel design methodology in general. This example assumes that you have familiarized yourself with the topic page, Channel Operating Margin (COM).

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Post-Layout Verification of PCIe 5.0 Allegro Board

Analyze a printed circuit board created in Cadence® Allegro, analyze multiple PCIe 5.0 lanes to determine which will have open or valid eye diagrams, and how to isolate and diagnose lanes with closed eye diagrams by back drilling vias. You can import the board, set it up for simulation by assigning parts, use EBD files for loopback boards, simulate at PCIe 5.0 data rate of 32 Gbps, and finally debug to fix a closed eye diagram.

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Crosstalk Analysis with Serial Link Designer

Perform pre-layout crosstalk analysis using the Serial Link Designer app.

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Explore Signal Integrity Interface with Design of Experiments and Response Surface Modeling

Setup and create a Design of Experiments (DOE) using the MATLAB® scripting interface in the Signal Integrity Toolbox™. You can simulate dozens of cases and use the Statistical and Machine Learning Toolbox™ to fit and analyze a linear model.

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