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Detect and Address Run-Time Errors

Detect design errors, generate counterexamples

Detect hidden design errors in your model, such as integer overflows or division by zero, early in the verification process. Perform design error detection analysis, review the analysis results, generate counterexamples to debug unintended functionalities, and then fix the identified design errors.


sldvextractExtract subsystem or subchart contents into new model for analysis
sldvoptionsCreate design verification options object
sldvrunAnalyze model
sldvreportGenerate Simulink Design Verifier report
sldvmakeharnessGenerate harness model