sldvoptions
Create Simulink Design Verifier options object
Description
Examples
Create an options object and set several parameters for the
sldvdemo_cruise_control model:
opts = sldvoptions; opts.Mode = "TestGeneration"; opts.ModelCoverageObjectives = "MCDC"; opts.ReportIncludeGraphics = "on"; opts.SaveHarnessModel = "off"; opts.SaveReport = "off"; opts.TestSuiteOptimization = "LongTestcases";
Get the options object for the
sldvdemo_cruise_control model. Use the
deepCopy method to create a standalone version of
sldvoptions starting with copy of options from the
model configuration set.
Open the model sldvdemo_cruise_control in command
prompt:
openExample("sldv/CruiseControlTestGenerationExample', ... 'supportingFile','sldvdemo_cruise_control"); optsModel = sldvoptions(bdroot); optsCopy = optsModel.deepCopy; optsCopy.MaxProcessTime = 120;
Input Arguments
Model name or handle, specified as a character vector or string scalar.
Output Arguments
This table lists the parameters that comprise a Simulink Design Verifier options object. The parameters are grouped by specific workflow and location in the Simulink Design Verifier options dialog box.
Note
When you set or retrieve parameters with set_param or
get_param, prefix
the option listed in this table with DV. For
example, to set option for test generation analysis, use this
command:
set_param("model_name","DVMode","TestGeneration")
| Pane | Parameter | Description | Values | |||||
|---|---|---|---|---|---|---|---|---|
| Design Verifier | Mode | Specify the analysis mode. |
| |||||
MaxProcessTime | Specify the maximum time (in seconds) that Simulink Design Verifier spends analyzing a model. You can set the value of maximum analysis time to the value that you are willing to provide to the analysis. You can also stop the analysis at any time. |
| ||||||
OutputDir | Specify a path name to which the Simulink
Design Verifier software writes its output. It also specifies
a directory in Simulink cache where Simulink Design Verifier write its
output. For example, you can use tokens such
as '$ to
represent the Simulink
Design Verifier cache folder. |
| ||||||
MakeOutputFilesUnique | Specify whether the software makes its output file names unique by appending a numeric suffix. |
| ||||||
RebuildModelRepresentation | Specify whether to rebuild the model representation for Simulink Design Verifier analysis. |
| ||||||
DesignMinMaxConstraints | Specify whether Simulink Design Verifier software generates test cases that consider specified minimum and maximum values as constraints for input signals in your model. |
| ||||||
ReduceRationalApprox | Specify whether to run additional analysis to reduce instances of rational approximation. |
| ||||||
UseParallel | Specify whether to validate test cases or counterexamples with parallel computing. This option requires a Parallel Computing Toolbox™ license. |
| ||||||
CovFilter | Specify whether to ignore objectives specified by coverage filter file for test generation and dead logic analysis. When set to |
| ||||||
CovFilterFileName | Specify the name of the folder and file name(s) that contain the objectives that you want to ignore from test generation and design error detection analysis. | character array
| ||||||
SFcnSupport | Specify to enable support for S-functions that have been compiled to be compatible with Simulink Design Verifier. |
| ||||||
CodeAnalysisIgnoreVolatile | Specify to ignore volatile qualifier
for the variables in S-Function. |
| ||||||
CodeAnalysisExtraOptions | Specify extra options to analyze S-functions that have been compiled to be compatible with Simulink Design Verifier. See Simulink Design Verifier Limitations and Considerations for S-Functions and C/C++ Code. | character array
| ||||||
| Block Replacements | BlockReplacement | Specify whether the software replaces blocks in a model before its analysis. When set to
|
| |||||
BlockReplacementRulesList | Specify a list of block replacement rules that execute before its analysis. This parameter
is enabled when | character array
| ||||||
BlockReplacementModelFileName | Specify a folder and file name for the model that is the result after applying block replacement rules. This parameter is enabled when
| character array
| ||||||
| Parameters and Variants | ParameterConfiguration | Specify how to configure parameters during Simulink Design Verifier analysis. You can select the parameters manually to configure or let Simulink Design Verifier automatically detect and configure these parameters. |
| |||||
ParameterNames | Specify parameter names in the Parameter Table. |
| ||||||
ParameterConstraints | Specify parameter constraints in the Parameter Table. |
| ||||||
ParameterUseInAnalysis | Specify parameters for which the parameter configuration is enabled in the Parameter Table. | cell array
| ||||||
ParametersConfigFileName | Specify a MATLAB® function that defines parameter configurations for a model. This parameter
is enabled when | character array
| ||||||
AnalyzeAllStartupVariants | Specify to analyze all variant blocks in
the model in a single analysis where the Variant
activation time parameter is set to
startup. |
| ||||||
| Test Generation | TestgenTarget | Specify the test generation target as model which
can be either |
| |||||
| Specify the type of model coverage to achieve. When
This parameter is enabled when Mode is set to Test Generation. |
| ||||||
TestConditions | Specify whether Test Condition blocks in your model are enabled or disabled. This parameter is
enabled when |
| ||||||
TestObjectives | Specify whether Test Objective blocks in your model are enabled or disabled. This parameter is
enabled when |
| ||||||
MaxTestCaseSteps | Specify the maximum number of simulation steps when attempting to satisfy a test objective. The
analysis uses the To achieve the best
performance, set the When you set the
This parameter is enabled when
|
| ||||||
TestSuiteOptimization | Specify the optimization strategy to use when generating test cases. This parameter is
enabled when |
| ||||||
IncludeRelationalBoundary | Specify generation of test cases that satisfy relational boundary objectives. |
| ||||||
AbsoluteTolerance | Specify an absolute value for the tolerance that is applied for signal or parameter values in relational boundary tests. | double
| ||||||
RelativeTolerance | Specify a relative value for tolerance to be applied for signal or parameter values in relational boundary tests. | cell array
| ||||||
StrictEnhancedMCDC | Specify whether to use strict propagation conditions for Enhanced Modified Condition Decision Coverage analysis. This parameter is enabled
when |
| ||||||
IgnoreCovSatisfied | Specify to analyze the model, ignoring satisfied
coverage objectives, as specified in
|
| ||||||
CoverageDataFile | Specify a folder and file name for the file that contains data about satisfied coverage objectives. This parameter is enabled when
| character array
| ||||||
ExtendExistingTests | Extend the Simulink Design Verifier analysis by importing test cases logged from a harness model or a closed-loop simulation model. When set to This
parameter is enabled when |
| ||||||
ExistingTestFile | Specify a folder and file name for the MAT file that contains the logged test case data. This parameter is enabled when
| character array
| ||||||
IgnoreExistTestSatisfied | Ignore the coverage objectives satisfied by the
logged test cases in
This
parameter is enabled when |
| ||||||
| Design Error Detection | DefectChecker | Specify to check for common and critical design errors such as division by zero, integer overflow, dead logic, and array out of bounds. The analysis detects only violations and does not report valid results. |
| |||||
DetectDeadLogic | Specify whether to analyze your model for dead logic. |
| ||||||
DetectActiveLogic | Specify whether to analyze your model for active logic. This parameter is enabled only if
|
| ||||||
DeadLogicObjectives | Specify the type of coverage objectives to be analyzed for dead logic in the model. |
| ||||||
DetectOutOfBounds | Specify whether to analyze your model for out of bounds array access errors. |
| ||||||
DetectDSMAccessViolations | Specify whether to analyze your model for data store access violations. |
| ||||||
DetectDivisionByZero | Specify whether to analyze your model for division-by-zero errors. |
| ||||||
DetectIntegerOverflow | Specify whether to analyze your model for integer and fixed-point data overflow errors. |
| ||||||
DetectInfNaN | Specify whether to analyze your model for non-finite and NaN floating-point values. |
| ||||||
DetectSubnormal | Specify whether to analyze your model for subnormal floating-point values. |
| ||||||
DesignMinMaxCheck | Specify whether to check that the intermediate and output signals in your model are within the range of specified minimum and maximum constraints. |
| ||||||
DetectBlockInputRangeViolations | Specify whether to analyze your model for block input range violations. |
| ||||||
DetectHISMViolationsHisl_0002 | Specify whether to check the usage of
|
| ||||||
DetectHISMViolationsHisl_0003 | Specify whether to check the usage of sqrt operations with inputs that can be negative. |
| ||||||
DetectHISMViolationsHisl_0004 | Specify whether to check the usage of
|
| ||||||
DetectHISMViolationsHisl_0028 | Specify whether to check the usage of Reciprocal sqrt blocks with inputs that can go zero or negative. |
| ||||||
| Property Proving | Assertions | Specify whether Assertion blocks in your model are enabled or disabled. |
| |||||
ProofAssumptions | Specify whether Proof Assumption blocks in your model are enabled or disabled. |
| ||||||
ProvingStrategy | Specify the strategy for proving properties. |
| ||||||
MaxViolationSteps | Specify the maximum number of simulation steps over which the software searches for property violations. This parameter is enabled
when |
| ||||||
| Results | DataFileName | Specify a folder and file name for the MAT file that contains the data generated during the analysis, stored in an sldvData structure. | character array
| |||||
SaveExpectedOutput | Specify to simulate the model by using test case signals and include the output values in the Simulink Design Verifier data file. |
| ||||||
RandomizeNoEffectData | Specify whether to use random values instead of zeros for input signals that have no impact on test or proof objectives. |
| ||||||
SaveHarnessModel | Specify to create a harness model generated by the Simulink Design Verifier analysis. When
When set to
|
| ||||||
HarnessSource | Specify the type of the Inputs block for the harness model. This parameter is enabled
when |
Note
| ||||||
HarnessModelFileName | Specify a folder and file name for the harness model. This parameter is enabled when
| character array
| ||||||
ModelReferenceHarness | Use a Model block to reference the model to run in the harness model. |
| ||||||
SlTestFileName | Specify name and path for test file name in Simulink Test™. | character array
| ||||||
SlTestHarnessName | Specify the name of the test harness in Simulink Test | character array
| ||||||
| Report | SaveReport | Specify to generate and save a Simulink Design Verifier report. When this parameter is
set to When set to
|
| |||||
ReportPDFFormat | Specify to generate additional report in PDF format. |
| ||||||
ReportFileName | Specify a folder and file name for the analysis report. This parameter is enabled when
| character array
| ||||||
ReportIncludeGraphics | Specify to include screen shots of properties in the report. This is applicable only in property proving analysis mode. This parameter is enabled
when |
| ||||||
DisplayReport | Specify to display the report that Simulink Design Verifier analysis generates after completing its analysis. This parameter is enabled when
|
|
Alternatives
Use the Configuration Parameters dialog box to set Simulink Design Verifier options. On the Design Verifier tab of the Simulink Toolstrip, click Test Generation Settings > Settings. Set analysis parameters in the Design Verifier pane of the Configuration Parameters dialog box. For more information, see Set Design Verifier Options Using the Configuration Parameters Dialog Box.
Version History
Introduced in R2007aSimulink
Design Verifier analysis produces an error when you set the harnessSource option to Signal Builder block.
See Also
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