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Hardware Implementation Pane

Hardware Implementation Pane Overview

Hardware board settings

ParameterDescriptionDefault Value
Processing UnitProcessor for model reference block in the SoC model.None

Design Mapping

ParameterDescriptionDefault Value
View/Edit Task Map

Open the task mapping tool.

not applicable
View/Edit Peripheral Map

Open the task mapping tool.

not applicable

Task profiling in simulation

ParameterDescriptionDefault Value
Show in SDI

Show the task execution data collected in simulation in the Simulation Data Inspector application.

on
Save to file

Save the task execution data to a file.

on
Overwrite file

Overwrite the last task execution data file.

off

Task profiling on processor

ParameterDescriptionDefault Value
Show in SDIShow the task execution data collected on hardware in the Simulation Data Inspector application.off
Save to fileSave the task execution data to a file.off
Overwrite fileOverwrite the last task execution data file.off
InstrumentationChoose to perform code instrumentation or Kernel instrumentation.Code
Profiling durationChoose whether to perform Kernel profiling for an unlimited or limited time duration.Unlimited

Operating system/scheduler

ParameterDescriptionDefault Value
Kernel latency

Specify the Kernel latency of the OS in simulation of a task.

0

Task and memory simulation

ParameterDescriptionDefault Value
Set seed for simulating task duration and memory accessSet the random number generator seed.off
Seed ValueSpecify the seed value for the simulation of task duration deviation.

default

Cache input data at task startCache the input data at the start of a task.

off

Board Parameters

ParameterDescriptionDefault Value
Device AddressNetwork address of hardware board or device.192.168.1.10
UsernameLogin username on hardware board or device.

root

PasswordLogin password on hardware board or device.

root

Processor

ParameterDescriptionDefault Value
Number of coresSet the number of CPU cores in the processor.1

Board Options

ParameterDescriptionDefault Value
Build Action

Defines how SoC Builder tool responds when you build your model.

Build, load, and run

Clocking

ParameterDescriptionDefault Value
CPU Clock (MHz)

The CPU clock frequency in MHz.

1000

External Mode

ParameterDescriptionDefault Value
Communication Interface

Transport layer used to exchange data between the development computer and hardware.

TCP/IP

Run external mode in a background thread

Execute the external mode engine in the generated code in a background task.

disabled

Port

IP address port on hardware board.

17725
Verbose

Enable view of the external mode execution progress and updates in the Diagnostic Viewer.

disabled

FPGA design (top-level)

ParameterDescriptionDefault Value
View/Edit Memory Map

Choose whether to perform global synthesis or per IP core synthesis.

Out of Context per IP

Include a JTAG master for host-based interaction

Use host-based scripts with an integrated JTAG master on the target platform.

on

Include processing system

For processor-based platforms, include the processing system.

on

Interrupt latency (s)

The latency from hardware asserting an interrupt to the start of the interrupt service routine.

0.00001

Register configuration clock frequency (MHz)

The system configuration clock drives the configuration register interfaces for the vendor IP cores in the system.

50

IP core clock frequency (MHz)

The clock for all Simulink® based generated HDL IP cores.

100

FPGA design (mem controllers)

ParameterDescriptionDefault Value
Controller clock frequency (MHz)

Frequency of datapath between memory interconnect and memory controller.

200

Controller data width (bits)

Bit width of datapath between memory interconnect and memory controller.

64

Bandwidth derating (%)

For every 100 clocks, will hold off all transaction execution for this number of clocks.

2.3

First write transfer latency (clocks)

Number of clock cycles between write request and start of transfer.

4

Last write transfer latency (clocks)

Number of clock cycles between the end of write transfer and completion of transaction.

4

First read transfer latency (clocks)

Number of clock cycles between read request and start of transfer.

5

Last read transfer latency (clocks)

Number of clock cycles between the end of read transfer and completion of transaction.

1

FPGA design (mem channels)

ParameterDescriptionDefault Value
Interconnect clock frequency (MHz)

Frequency of the master datapath to the interconnect controller in MHz.

200

Interconnect data width (bits)

Data width of master datapath to interconnect controller in bits.

64

Interconnect FIFO depth (num bursts)

Maximum number of bursts that can be buffered before data is dropped.

12

Interconnect almost-full depth

When the almost full depth is reached, the attached channel protocol interface block asserts back pressure to the data source.

8

FPGA design (debug)

ParameterDescriptionDefault Value
Memory channel diagnostic level

The internal operation of the memory channel can be instrumented for debug or diagnostic analysis.

Basic diagnostic signals

Include AXI interconnect monitor

Gather performance metrics of the memory interconnect such as data throughput, latency, and number of bursts executed.

off

Trace capture depthMaximum number of Trace entries to be logged in trace mode

1024