Read data from a register region on the specified IP core
SoC Blockset / Processor I/O
The Register Read block reads data from a register region on the specified IP core. In simulation, a timer-driven or event-driven task subsystem contains the Register Read block. The data signals from the Register Read block connect to the Register Channel block managing those registers and their transactions.
When developing or analyzing the software side of an SoC application, the Register Read block can be connected to an IO Data Source block. In this configuration, the IO Data Source block provides either previously recorded or artificial data, enabling a more directed simulation of the software and processor side of the application, without need to explicitly model the hardware and memory interactions.
msg— Data message from register
This port receives the data messages from the connected Register Channel or IO Data Source block. The messages process when the Task Manager block triggers task containing the Register Read block. The input port receives data messages from a Register Channel or IO Data Source block as entities. For more information on entities, see Entities in an SoC Blockset Model.
Device name— Path and file name of IP core device
/dev/mwipcore(default) | character array
Enter the path and file name of the IP core device.
Offset address— Offset from the base address of the IP core to the register
hex2dec('0100')(default) | positive integer
Output data type— Data type used by IP core
Enter the data type used by the IP core.
Output vector size— Size of data vector from IP core
1(default) | positive integer
Enter the size of the data vector read from the IP core device.
To automatically generate C code for your design, and execute on an SoC device, use the SoC Builder tool. See Generate SoC Design. You must have an Embedded Coder® license to generate and execute C code for your SoC device.
SoC Builder implements the Register Read block with FPGA and processor IPs that use the AXI4 interface protocol. The AXI4 interface protocol allows the processor algorithm to read vector data from a contiguous group of registers on the FPGA. Use this block for simple, low-throughput memory-mapped communication, such as reading from control and status registers. This diagram shows a generalized representation of the generated code implementation.