# N-Channel LDMOS FET

N-Channel laterally-diffused metal-oxide-semiconductor or vertically-diffused metal-oxide-semiconductor transistors suitable for high voltage

**Libraries:**

Simscape /
Electrical /
Semiconductors & Converters

## Description

The N-Channel LDMOS FET block models LDMOS (or VDMOS) transistors suitable for high voltage. The model is based on surface potential and includes effects due to an extended drain (drift) region:

Nonlinear capacitive effects associated with the drift region

Surface scattering and velocity saturation in the drift region

Velocity saturation and channel-length modulation in the channel region

Charge conservation inside the model, so you can use the model for charge sensitive simulations

The intrinsic body diode

Reverse recovery in the body diode model

Temperature scaling of physical parameters

For the option with exposed thermal ports (see Thermal Port), dynamic self-heating

This figure shows the physical structure of the model:

The channel region is in the p+ region, from the heavily n-doped source well to the end of the p+ region. The drift region is a lightly doped drain extension. Further down, there is a p-type epi-layer, and then the entire structure is on a heavily p-doped substrate. The gate oxide is thin over the entire channel region and over part of the drift region. Further into the drift region, the gate oxide has a greater thickness in the local-oxidation-of-silicon (LOCOS) region.

This figure shows the equivalent circuit of the model.

The modeling approach is similar to [1]. The overlaps of the gate contact with the source and drain n-wells are modeled as lumped linear capacitances. The channel (p+) region is modeled using the surface-potential-based MOSFET model. The pn-junction between the source/bulk and drain is modeled using an ideal diode, including both junction and diffusion capacitances. The drift region underneath the thin gate oxide is modeled according to a surface-potential formulation, which includes:

The current due to the accumulation layer at the semiconductor-oxide interface

The current due to the electrons flowing towards the drain deeper inside the drift region

The space-charge region between the epi-layer and the drift region is represented using a pinching effect on the current flowing through the bulk of the drift region. The LOCOS part of the drift region is modeled as a lumped, series resistor, and there are also series resistances added to the source and gate contacts.

For detailed description of the channel model, see the surface-potential-based model of the N-Channel MOSFET block. The drift region model is similarly derived from the surface potential using the Poisson equation. For an n-type semiconductor under the gradual-channel approximation, the defining equations are:

$$\frac{{\partial}^{2}\psi}{\partial {y}^{2}}\approx \frac{q{N}_{D}}{{\epsilon}_{Si}}\left[-1-\mathrm{exp}\left(\frac{-\psi -2{\varphi}_{B}}{{\varphi}_{T}}\right)+\mathrm{exp}\left(\frac{\psi -{V}_{CB}}{{\varphi}_{T}}\right)\right]$$

$${\varphi}_{T}=\frac{{k}_{B}T}{q}$$

where:

*ψ*is the electrostatic potential.*q*is the magnitude of the electronic charge.*N*is the doping density of the drift region._{D}*ɛ*is the dielectric permittivity of the semiconductor material (for example, silicon)._{Si}*ϕ*is the difference between the intrinsic Fermi level and the Fermi level deep in the drift region._{B}*V*is the quasi-Fermi potential of the drift region referenced to the bulk._{CB}*ϕ*is the thermal voltage._{T}*k*is Boltzmann’s constant._{B}*T*is temperature.

Neglect the inversion for the DC current model to obtain this current expression,

$${I}_{D}=\frac{1}{1+{\theta}_{sat}{V}_{DK}}\left[\frac{{f}_{lin}}{{R}_{D}}{V}_{DK}+\frac{\beta}{2}\cdot \frac{{V}_{GK}^{2}-{V}_{GD}^{2}}{1+\frac{{\theta}_{surf}}{2}\left({V}_{GK}+{V}_{GD}\right)}\right]$$

where:

*I*is the drain current._{D}*θ*is the velocity saturation._{sat}*V*is the voltage difference between nodes_{ij}*i*and*j*, where subscripts D and K refer to the drain and to the junction of the channel and drift regions, respectively, and subscript G refers to the gate with a correction due to the flatband voltage being applied.*f*/_{lin}*R*represents the conductance of the bulk of the drift region, including the effect of pinching due to depletion from the epi-drift interface._{D}*β*is the gain of the accumulation layer at the interface between the drift region and the thin gate oxide.*θ*is the parameter that accounts for scattering in the accumulation layer due to the vertical electric field._{surf}

This equation describes the pinching off of the bulk part of the drift region,

$${f}_{lin}=1-{\lambda}_{D}\frac{\sqrt{{V}_{bi}+{V}_{SB}}-\sqrt{{V}_{bi}}}{\sqrt{{V}_{bi}}}$$

where:

*λ*is the parameter representing the n-side vertical depth of the space-charge region along the epi-drift interface at zero bias divided by the vertical depth of the undepleted part of the drift region at zero bias._{D}In the figure, the top solid line is the semiconductor surface. The lower solid line is the junction between the drift region and the epi layer. The dashed lines show the extent of the space-charge region around the drift-epi interface.

*λ*is_{D}*y*/_{1}*y*at zero bias._{2}*V*is the built-in voltage for the epi-drift diode._{bi}*V*is the source-body voltage, used as an approximation to the bias applied across the epi-drift diode. Using this voltage instead of_{SB}*V*is more numerically stable, and is justified because most of the drain-source voltage drops across the drift region in the transistor on-state._{KB}

The charge model is similar to that of the surface-potential-based MOSFET model, with additional expressions to account for the charge in the drift region. The block uses the derived equations as described in [1], which include both inversion and accumulation in the drift region.

### Modeling Body Diode

The block models the body diode as an ideal, exponential diode with both junction and diffusion capacitances:

$${I}_{dio}={I}_{s}\left[\mathrm{exp}\left(-\frac{{V}_{DB}}{n{\varphi}_{T}}\right)-1\right]$$

$${C}_{j}=\frac{{C}_{j0}}{\sqrt{1+\frac{{V}_{DB}}{{V}_{bi}}}}$$

$${C}_{diff}=\frac{\tau {I}_{s}}{n{\varphi}_{T}}\mathrm{exp}\left(-\frac{{V}_{DB}}{n{\varphi}_{T}}\right)$$

where:

*I*is the current through the diode._{dio}*I*is the reverse saturation current._{s}*V*is the drain-body voltage._{DB}*n*is the ideality factor.*ϕ*is the thermal voltage._{T}*C*is the junction capacitance of the diode._{j}*C*is the zero-bias junction capacitance._{j0}*V*is the built-in voltage._{bi}*C*is the diffusion capacitance of the diode._{diff}*τ*is the transit time.

The capacitances are defined through an explicit calculation of charges, which are then differentiated to give the capacitive expressions above. The block computes the capacitive diode currents as time derivatives of the relevant charges, similar to the computation in the surface-potential-based MOSFET model.

### Modeling Temperature Dependence

The default behavior is that dependence on temperature is not modeled, and the
device is simulated at the temperature for which you provide block parameters. To
model the dependence on temperature during simulation, select ```
Model
temperature dependence
```

for the
**Parameterization** parameter on the **Temperature
Dependence** tab.

The model includes temperature effects on the capacitance characteristics, as well as modeling the dependence of the transistor static behavior on temperature during simulation.

The **Measurement temperature** parameter on the
**Main** tab specifies temperature
*T _{m1}* at which the other device
parameters have been extracted. The

**Temperature Dependence**parameters provides the simulation temperature,

*T*, and the temperature-scaling coefficients for the other device parameters. For more information, see Temperature Dependence.

_{s}### Thermal Port

You can expose the thermal port to model the effects of generated heat and device
temperature. To expose the thermal port, set the **Modeling option**
parameter to either:

`No thermal port`

— The block does not contain a thermal port and does not simulate heat generation in the device.`Show thermal port`

— The block contains a thermal port that allows you to model the heat that conduction losses generate. For numerical efficiency, the thermal state does not affect the electrical behavior of the block.

For more information on using thermal ports and on the **Thermal Port**
parameters, see Simulating Thermal Effects in Semiconductors.

The thermal option of this block includes dynamic self-heating. This lets you simulate the effect of self-heating on the electrical characteristics of the device.

### Variables

To set the priority and initial target values for the block variables before simulation,
use the **Initial Targets** section in the block dialog box or Property
Inspector. For more information, see Set Priority and Initial Target for Block Variables.

Use nominal values to specify the expected magnitude of a variable in a model. Using
system scaling based on nominal values increases the simulation robustness. Nominal values
can come from different sources. One of these sources is the **Nominal
Values** section in the block dialog box or Property Inspector. For more
information, see System Scaling by Nominal Values.

### Plot Basic I-V Characteristics

You can plot the basic I-V characteristics of the N-Channel LDMOS FET block without building a complete model. Use the plots to explore the impact of your parameter choices on device characteristics. If you parameterize the block from a datasheet, you can compare your plots to the datasheet to check that you parameterized the block correctly. If you have a complete working model but do not know which manufactured part to use, you can compare your plots to datasheets to help you decide.

To enable this option, set the **Modeling option** parameter of the
N-Channel LDMOS FET block to `No thermal port`

. To plot the basic
characteristics, right-click the block and select **Electrical** >
**Basic characteristics** from the context menu. For more
information about the **Basic characteristics** option, see Plot Basic I-V Characteristics of Semiconductor Blocks.

## Ports

### Conserving

## Parameters

## References

[1] Aarts, A., N. D’Halleweyn, and R. Van Langevelde. “A
Surface-Potential-Based High-Voltage Compact LDMOS Transistor Model.”
*IEEE Transactions on Electron Devices*. 52(5):999 - 1007. June
2005.

[2] Van Langevelde, R., A. J. Scholten, and D. B. M. Klaassen.
"Physical Background of MOS Model 11. Level 1101."* Nat.Lab. Unclassified
Report 2003/00239*. April 2003.

[3] Oh, S-Y., D. E. Ward, and R. W. Dutton. “Transient
analysis of MOS transistors.” *IEEE J. Solid State
Circuits*. SC-15, pp. 636-643, 1980.

## Extended Capabilities

## Version History

**Introduced in R2016b**