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Intel FPGA Board Support from HDL Verifier

HDL Verifier™ automates the verification of HDL code on FPGA boards by providing connections between your FPGA board and your simulations in Simulink® or MATLAB®.

  • FPGA-in-the-loop (FIL) enables you to run a Simulink or MATLAB simulation that is synchronized with an HDL design running on an FPGA board.

  • FPGA data capture is a way to observe signals from your design while the design is running on the FPGA. It captures a window of signal data from the FPGA, based on your configuration and trigger settings, and returns the data to MATLAB or Simulink.

  • AXI manager provides access to live on-board memory locations from Simulink or MATLAB. You must include the AXI manager IP in your FPGA design.

To use each of these features, you must have a supported FPGA board connected to your MATLAB host computer using a supported connection type, and a supported synthesis tool.

Supported Intel FPGA Boards

This support package enables FIL simulation for the boards in the table. FPGA data capture and AXI manager are available on those boards that have JTAG USB Blaster I or USB Blaster II connections.

Device FamilyBoardEthernetJTAGPCI ExpressComments
FILFPGA Data CaptureAXI ManagerFILFPGA Data CaptureAXI ManagerFILaFPGA Data CaptureAXI Manager

Intel® Arria® II

Arria II GX FPGA Development Kitx xxxx  x 

Intel Arria V

Arria V SoC Development Kit  xxxx    
Arria V Starter Kitx xxxx  x 

Intel Arria 10

Arria 10 SoC Development Kitx xxxx    
Arria 10 GXx xxxxx x

Quartus® Prime 18.0 is not recommended for Arria 10 GX over PCI Express®.

Intel Cyclone® IV

Cyclone IV GX FPGA Development Kitx xxxx  x
DE2-115 Development and Education Boardx xxxx   The Altera® DE2-115 FPGA development board has two Ethernet ports. FIL uses only Ethernet 0 port. Make sure that you connect your host computer with the Ethernet 0 port on the board via an Ethernet cable.
BeMicro SDKx xxxx    

Intel Cyclone III

Cyclone III FPGA Starter Kitx xxxx   

Altera Cyclone III boards are supported with Quartus II 13.1

Note

Support for Cyclone III device family will be removed in a future release.

Cyclone III FPGA Development Kitx xxxx   
Altera Nios II Embedded Evaluation Kit, Cyclone III Editionx xxxx   

Intel Cyclone V

Cyclone V GX FPGA Development Kitx xxxx  x 
Cyclone V SoC Development Kit   xxxx    
Cyclone V GT Development Kitx xxxxx x 
Terasic Atlas-SoC Kit / DE0-Nano SoC Kit  xxxx    
Arrow® SoCKit Development Kit  xxxx    

Intel Cyclone 10 LP

Altera Cyclone 10 LP Evaluation Kit

  xxxx    

Intel Cyclone 10 GX

Altera Cyclone 10 GX FPGA Evaluation Kit

  xxxx  x

Must be used with Quartus Prime Pro

Intel MAX® 10

Arrow MAX 10 DECA

x xxxx    

Intel Stratix® IV

Stratix IV GX FPGA Development Kitx xxxx  x 

Intel Stratix V

DSP Development Kit, Stratix V Editionx xxxxx x 

a FIL over PCI Express connection is supported only for 64-bit Windows® operating systems.

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