Convert video stream to YCbCr 4:2:2 pixel stream
SoC Blockset Support Package for Xilinx Devices / Video
The HDMI Rx block converts raw video data to a YCbCr 4:2:2 pixel stream format. It can return data in pixel stream mode for hardware algorithm design or in frame mode for faster simulation. When you include this block in your design, the SoC Builder tool generates all the IP blocks necessary to receive video data from the FMC-HDMI-CAM card attached to your hardware board. None of the block parameters affect hardware behavior. When simulating, specify a video file to stream.
You must have Computer Vision Toolbox™ to use this block.
hdmiRxData — Single YCbCr 4:2:2 pixel in pixel stream
concatenated YCbCr value
Single YCbCr 4:2:2 pixel in pixel stream, specified as a scalar in concatenated YCbCr 4:2:2 format, where
bits [1:8] represent Y.
bits [9:16] represent Cb or Cr, interleaved in time.
ctrl — Control signals accompanying output pixel stream
Control signals accompanying output pixel stream, returned as a
pixelcontrol (Vision HDL Toolbox) bus. The bus contains five
Boolean signals indicating the validity of a pixel and its location
within a frame.
When the Output mode parameter is
Frame, the block sets all five signals in
pixelcontrol bus to
indicate when the output data is valid.
Frame size — Video frame size
160x120p (default) |
Pixel | ...
Select the video frame size as one of these values:
480p SDTV (720x480p)
576p SDTV (720x576p)
720p HDTV (1280x720p)
1080p HDTV (1920x1080p)
Output mode — Output mode of the block
Frame (default) |
Specify whether the output is streamed one pixel per clock cycle or one
frame per clock.
Pixel mode better represents the
hardware algorithm and is recommended for FPGA deployment.
Frame mode enables faster simulation.
Input file name — Input video file
Specify the full path to an input video file. For information on the supported file types, see From Multimedia File (Computer Vision Toolbox).
Frame sample time — Block sample time
1/60 (default) | positive scalar
Block sample time, in seconds, specified as a positive scalar. The default value corresponds to a frame rate of 60 fps.
Visualize input frame — Display input video
on (default) |
Selecting this option enables a To Video Display (Computer Vision Toolbox) block to display the input frame during simulation.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool.
Introduced in R2019a