This example shows how to deploy the system information block 1 (SIB1) recovery algorithm from the NR HDL Downlink Receiver MATLAB Reference (Wireless HDL Toolbox) example as a hardware-software (HW/SW) co-design implementation targeted on the Analog Devices AD9361/AD9364 radio platform. Using this implementation, you can perform SIB1 recovery from off-the-air 5G NR waveforms.
For a list of supported radio hardware platforms, see Hardware Support. This example does not support Avnet Zedboard and FMCOMMS2/3/4. The algorithm requires more hardware resources than are available on these boards.
This example deploys a SIB1 recovery algorithm as a hardware-software (HW/SW) co-design implementation targeted on the Analog Devices AD9361/AD9364 radio platform. This example is one of a related set of examples, which show the workflow for designing and deploying a 5G NR cell search, MIB recovery and SIB1 recovery algorithm to hardware. This figure shows the complete workflow.
The MATLAB Golden Reference Algorithm step consists of the NR Cell Search and MIB and SIB1 Recovery (5G Toolbox) example, which shows the floating-point golden reference algorithm.
The MATLAB Hardware Reference Algorithm step consists of the NR HDL Downlink Receiver MATLAB Reference (Wireless HDL Toolbox) example, which models hardware-friendly algorithms and generates test waveforms. This MATLAB® code operates on vectors and matrices of floating-point data samples and does not support HDL code generation.
The Simulink Fixed-Point Implementation Model step consists of multiple examples. The NR HDL Cell Search (Wireless HDL Toolbox) example demonstrates a 5G cell search Simulink® subsystem that uses the same algorithm as the MATLAB reference. The NR HDL MIB Recovery (Wireless HDL Toolbox) example adds a broadcast channel decoding and MIB recovery subsystem. The NR HDL SIB1 Recovery (Wireless HDL Toolbox) example adds a subsystem that recovers the SIB1 resource grid, and shows how to decode its output using MATLAB reference code. The NR HDL MIB Recovery for FR2 (Wireless HDL Toolbox) example shows cell search and MIB recovery models which have been extended to support FR2. These models operate on fixed-point data and are optimized for HDL code generation.
The Simulink SoC Deployment Model step consists of the 5G NR SIB1 Recovery Using Analog Devices AD9361/AD9364 example (this example), which deploys the SIB1 Recovery FR1 design to the Analog Devices AD9361/AD9364 radio platform. For a list of additional examples that demonstrate this step, see Deploy NR HDL Reference Applications on SoCs (Wireless HDL Toolbox).
For a general description of how to use MATLAB and Simulink® to develop deployable models, see Wireless Communications Design for FPGAs and ASICs.
This figure shows a conceptual overview of the SIB1 recovery algorithm.
The SSB Detector, SSB Decoder, and SIB1 Grid Demodulator perform the high-speed signal processing tasks required to detect, demodulate, and decode 5G NR synchronization signal blocks (SSB), and OFDM demodulate the part of the resource grid which contains SIB1. This makes these parts well suited for FPGA implementation on the programmable logic (PL) of the radio platform. To implement the detector and decoder in the PL, the example uses model references of the Simulink hardware models from the NR HDL Cell Search (Wireless HDL Toolbox) and NR HDL MIB Recovery (Wireless HDL Toolbox) reference examples, respectively.
The Search Controller coordinates the operation of the detector and decoder hardware cores and operates at a low rate. This makes the search controller well suited for software implementation on the integrated ARM® processing system (PS) of the radio platform. The example uses the Search Controller algorithm described in the NR HDL Downlink Receiver MATLAB Reference (Wireless HDL Toolbox) example.
The SIB1 Decoder is the final stage in SIB1 recovery and decodes the downlink control information (DCI) and SIB1 payload. Implementing this stage in software results in a flexible design. The SIB1 Decoder can be modified or replaced with an alternative processing step and redeployed to hardware rapidly without the need to rebuild the FPGA bitstream.
To work with the HW/SW co-design workflow, you must install and configure additional support packages and third-party tools. For more information, see Installation for Hardware-Software Co-Design.
This Simulink model is a hardware generation model of the combined SSB Detector, SSB Decoder and SIB1 Grid Demodulator for targeting SDR platforms. From this model, you can generate HDL code for the PL and generate a template software interface model using HDL Workflow Advisor. Using the template software interface model, you can generate an application that runs on the PS. This diagram shows the hardware subsystem and a simple test harness.
5G SIB1 Recovery HDL subsystem adopts the SIB1 recovery model from the NR HDL SIB1 Recovery (Wireless HDL Toolbox) example and adds additional functionality to integrate the model with the Zynq® hardware architecture.
SSB Report Interface subsystem generates primary synchronization signal (PSS) reports with the five numerical values of
pssSignalThreshold and formats them into a custom packet forma. The packets are sent over DMA to the controller on the ARM. Each standard-size packet consists of up to 48 PSS reports and an entry defining the number of valid reports in the packet.
AXI-Stream Manager subsystem formats the SSB and SIB1 grids for transmission to the PS via DMA. The SIB1 Grid Recovery algorithm outputs the SSB grid followed by the SIB1 grid so a single connection is shared for both sets of grid data. The SSB grid is a fixed size of 960 elements (240 subcarriers by 4 OFDM symbols). Due to the variable bandwidths of the SIB1 grid the transmission size depends on the bandwidth. Additionally, for SCS 15 the SIB1 grid is transmitted one slot at a time over two subsequent packets. SCS 30 transmits both slots in one packet.
Simulate Hardware Generation Model
To confirm basic operation, you can run the hardware generation model using a synthetic 5G NR waveform. You can generate a waveform using the
nrhdlexamples.generateFR1RxWaveform function. The model calls this function in the initialization callback and assigns the waveform to the workspace variable
sib1Waveform. You can find the initialization callback in MODELING > Model Settings > Model Properties > Callbacks > InitFcn. As the model contains a large number of HDL-optimized blocks requiring simulation using sample-based signals, full simulation can take a while.
To model the RF front end, the test harness uses the generated 5G NR waveform as an input. You can switch between simulating the model in search or demodulation modes by double clicking on the manual switch block. In search mode, the model reaches
detectionStatus state 3, which means a PSS is found. The search produces a PSS report for each PSS found. These reports are zero-padded to 244 entries and logged to the MATLAB workspace. In demodulation mode, the model reaches
detectionStatus state 8 indicating that the SSB is demodulated and its secondary synchronisation signal (SSS) is found. Once the
detectionStatus reaches state 8, the model starts processing the MIB.
bchStatus state 4 indicates that the MIB is successfully recovered. After the MIB is recovered the SIB1 grid demodulation stage starts.
sib1DemodStatus state 2 indicates that the SIB1 grid is outputting. The model returns the demodulated SSB and SIB1 OFDM grids in the MATLAB workspace. In addition, the model also returns the zero-padded 244-entry PSS report.
When the simulation behavior of the hardware subsystem is satisfactory, you can start the process of generating the HDL IP Core, integrating it with the SDR reference design, and generating software for the ARM processor.
Start the targeting workflow by right-clicking the
5G SIB1 Recovery HDL subsystem and selecting HDL Code > HDL Workflow Advisor.
In Step 1.1, select the
IP Core Generation workflow and the appropriate Zynq radio platform:
ADI RF SOM,
ZC706 and FMCOMMS2/3/4,
ZCU102 and FMCOMMS2/3/4, or
ZC706 and FMCOMMS5. This example does not support Avnet Zedboard and FMCOMMS2/3/4. The algorithm requires more hardware resources than are available on these boards.
In Step 1.2, select the
Receive path reference design. For this example, you can use default reference design parameters.
In Step 1.3, the interface table maps the DUT signals to the interface signals available in the reference design. Because this example uses a single channel, configure the channel 1 connections and AXI register interfaces as shown in these images.
In Step 1.4, set the DUT synthesis frequency. The DUT synthesis frequency depends on the baseband sampling rate of the system. The MIB Recovery algorithm implementation in this example is built for a sampling rate value of 61.44 MHz.
Step 2 prepares the model for HDL code generation by performing design checks.
Step 3 generates HDL code for the IP core.
Step 4 of the HDL Workflow Advisor integrates the newly generated IP core into the Zynq SDR reference design, generates the corresponding bitstream, and loads the bitstream onto the board.
Step 4.2 generates a software interface library and a template software interface model.
Software Interface Library
The library contains the AXI Interface block generated from the
5G SIB1 Recovery HDL subsystem and a receiver block corresponding to your hardware you selected in Step 1.1. The data ports of the receiver block represent the DMA interface between the FPGA user logic and the ARM processor. The DMA interface is used to stream the OFDM demodulated symbols of the MIB and SIB1 grids to the ARM processor after demodulation. The maximum transmission is 576 subcarriers by 28 OFDM symbols so the frame size is set to 16128.
To stream the grids from the SIB1 Recovery algorithm (running on hardware) to the search controller algorithm (running on software), the model utilizes an AXI4-Stream interface. The AXI4-Stream IIO Read (Embedded Coder Support Package for Xilinx Zynq Platform) block which implements the AXI4-Stream interface in the software interface model is not generated in the template or library. You must add the block from the Simulink Library Browser > Embedded Coder Support Package for Xilinx Zynq Platform library.
When using the library blocks in a downstream model, you must configure the parameters correctly for your application. Take into account that any updates to the
5G SIB1 Recovery HDL subsystem are automatically propagated to the library blocks in the downstream model when you run Step 4.2 again.
Template Software Interface Model You can use the generated template software interface model as a starting point for full SW targeting in, for example, external mode simulation, or full deployment. Because HDL Workflow Advisor overwrites the generated model each time you run Step 4.2, consider saving the generated model under a unique name and develop your software algorithm there.
The last steps of the HDL Workflow Advisor generate a bitstream for the PL and download the bitstream onto the board.
Step 4.3 generates a bitstream for the PL. You can execute this step in an external shell by selecting Run build process externally. This selection allows you to continue using MATLAB while building the FPGA image. Once some basic project checks are complete, Step 4.3 is marked with a green checkmark. However, you must wait until the external shell displays a successful bitstream build before moving on to the next step.
Step 4.4 downloads the bitstream onto the device. Before continuing with this step, make sure that MATLAB is set up with the correct physical IP address of the radio hardware by calling the
>> devzynq = zynq('linux','192.168.3.2','root','root','/tmp');
By default, the physical IP address of the radio hardware is 192.168.3.2. If you alter the radio hardware IP address during the hardware setup process, you must supply that address instead.
Alternatively, if you want to load the bitstream outside HDL Workflow Advisor, create an SDR radio object and use the
downloadImage function. The radio object to create depends on the radio platform selected in Step 1.1.
If the selected radio platform is either
ADI RF SOM,
ZC706 and FMCOMMS2/3/4, or
ZCU102 and FMCOMMS2/3/4, create an AD936x radio object.
radio = sdrdev('AD936x');
If the selected radio platform is
ZC706 and FMCOMMS5, create an FMCOMMS5 radio object.
radio = sdrdev('FMCOMMS5');
Download the bitstream using the radio object interfacing the selected radio device.
downloadImage(radio,'FPGAImage', ... 'hdl_prj\vivado_ip_prj\vivado_prj.runs\impl_1\system_top.bit') % Path to the generated bitstream
The 5G NR SIB1 Recovery software interface model is based on the generated template software interface model. This model coordinates the SIB1 grid recovery, as described in the NR HDL Downlink Receiver MATLAB Reference (Wireless HDL Toolbox) example.
Cell Search Controller block controls the deployed hardware model by using the AXI4-Lite and AXI4-Stream interfaces inside the
SIB1 Recovery subsystem. The controller instructs the FPGA design to search for cells over a range of frequencies and subcarrier spacings and then starts the process of demodulating a selected cell.
SIB1 Processing subsystem runs the SIB1 decoding alogorithm. This consists of two stages, decoding the physcial downlink control channel(PDCCH) and the physical downlink shared channel (PDSCH). The status of each stage is reported, including the success of the operation. The SIB1 Processing subsystem runs at a lower rate and on a seperate thread from the rest of the software. This allows for the complex decoding to complete without blocking the remaining software. Rate transition blocks are inserted on the boundaries to facilitate data transfer between the threads.
UDP send grid,
UDP send PSS report,
UDP send SSS report,
UDP send MIB report, and
UDP send SIB1 report subsystems relay the demodulated OFDM grid data, PSS report, SSS report, MIB report, and SIB1 report, respectively, to the host by using the UDP protocol.
The model is configured for the
Xilinx Zynq-7000 Based Board target. You can use this target for the
ADI RF SOM or
ZC706 and FMCOMMS2/3/4/5 radio platforms. For the
ZCU102 and FMCOMMS2/3/4 radio platform, you must reconfigure the model by selecting
Zynq UltraScale+ MPSoC ZCU102 IIO Radio in Model Settings (Ctrl+E) > Hardware Implementation > Hardware board or by double clicking the provided
Select Hardware Board Target block.
You can use the scopes from the software interface model to monitor the hardware and software. The
Algorithm Scope plots the progress of the cell search algorithm, and the
SIB1 Status Scope shows the progress of the software SIB1 decode.
The periodic software start signal begins each operation.
The controller instructs the PL to perform SSB detection in search mode (Hardware Mode 0) for each coarse frequency step and subcarrier spacing. The scope shows how the Frequency Offset and Subcarrier Spacing signals are set for each search attempt and how the Hardware Start signal is pulsed to begin.
The controller selects a coarse frequency offset and subcarrier spacing based on the PSS correlation strength and residual fine frequency offset of detected SSBs. A final search runs with the combined coarse and fine frequency corrections.
A demod mode (Hardware Mode 1) operation starts. This attempts to reacquire the best SSB from the previous search, demodulate the resource grid, and compute the cell ID from the SSS sequence.
detectionState reaches 8, indicating the SSB OFDM grid has been demodulated and the SSS determined, the hardware decodes the SSB. The
decodingState then reaches state 4, indicating successful decoding.
The hardware demodulates the SIB1 grid and sends it to the software. The
sib1GridStatus reaches state 2 indicating that the grid is being transfered.
The software extracts the SIB1 grid data from the interface shared with the SSB grid data transfer, and the SIB1 grid is reconstructed.
The PDCCH decoding and DCI search are performed on the SIB1 grid to recover the DCI message. When PDCCH processing is complete the
pdcchdone signal is asserted and the
dciCRC signal indicates the status of the DCI CRC (0 indicates successful decode, 1 indicates an error).
On successful recovery of the DCI message PDSCH decoding is performed to recover the SIB1 message. When PDSCH processing is complete the
pdschdone signal is asserted and the
sib1CRC signal indicates the status of the CRC for the SIB1 message (0 indicates successful decode, 1 indicates an error). The recovered SIB1 message bits are output from the PDSCH processing stage.
For more information about the algorithm, see NR HDL Downlink Receiver MATLAB Reference (Wireless HDL Toolbox). In some instances, the hardware state can change faster than the polling of the AXI-Lite registers, so transitions may be missed.
In this example, the
SIB1 Scope displays a selection of additional information. To view signals of interest, you can customize the model. For further exploration, you can add postprocessing subsystems to perform live analysis of the returned signals.
You can run the 5G NR SIB1 Recovery software interface model in
Monitor & Tune mode. In this mode, you can control the configuration from the Simulink model. Alternatively, to deploy the design on the board disconnected from Simulink, click
Build Deploy & Start.
The default center frequency for this example is 3.42048 GHz. You can adjust the center frequency by using the
Center Frequency constant block.
Start/Restart Pulse Generator block resets the cell search controller algorithm with a period of 0.6 seconds.
Host Interface Model
The ARM sends the demodulated SSB OFDM grid data, PSS reports, SSS reports, MIB reports, and SIB1 reports directly back to the host over the Ethernet link by using UDP send blocks. The IP address of the UDP send block must be the IP address of the host, by default,
'192.168.3.1'. If you alter the IP address during the hardware setup process, you should supply that address instead.
This interface model, which runs on the host, illustrates how to receive data from the hardware platform and how to postprocess it. You can use the rocker switch to select between automatically stopping the model after SIB1 is recovered or to receive indefinitely.
When the host interface model successfully runs, the model displays the received signal-to-noise ratio (SNR) of the PSS and SSS in dB, the cell ID, the contents of the recovered MIB, and the number of SIB1 recoveries. While the model continuously runs, the MIB counts increment for each successful recovery.
Additionally, the count of successful SIB1 recoveries is displayed.
For further processing, the model also exports five timeseries variables to the MATLAB workspace:
If you are unable to receive a strong 5G signal in your location, consider performing a loopback of the generated waveform by using the
transmitRepeat function. The sythesized waveform does not include the effects of phase pre-compensation so the rocker switch enablePhaseComp needs to be set to 0.
set_param('zynqRadioHWSW5GNRSIB1RecoveryAD9361AD9364SL_interface/enablePhaseComp','sw','0'); % Generate 5G waveform [txWaveform,~,~] = nrhdlexamples.generateFR1RxWaveform('SimCase 1'); % Create a transmitter System object for the AD936x-based radio hardware and set desired radio settings. tx = sdrtx('AD936x', 'CenterFrequency', 3560e6, 'BasebandSampleRate', 61.44e6, 'IPAddress', '192.168.3.2'); % Send waveform to the radio and repeatedly transmit it. transmitRepeat(tx,txWaveform);
The host interface model returns the demodulated OFDM grid data to the MATLAB workspace. If you have a strong signal, consider plotting this grid. For example:
gridFormatData = squeeze(sl_grid.Data); y = reshape(gridFormatData(:,1),[240,4]); gridData = double(abs(y)); OFDMGridFigure = figure('Name','OFDM Grid'); axes1 = axes('Parent',OFDMGridFigure); hold(axes1,'on'); imagesc(gridData,'Parent',axes1,'CDataMapping','scaled'); ylabel('Subcarrier'); xlabel('OFDM Symbol'); title('5G NR OFDM Demodulated Grid'); box(axes1,'on'); axis(axes1,'ij'); hold(axes1,'off'); set(axes1,'Layer','top',... 'XTick',[1 2 3 4],'YTick',[1 40 80 120 160 200 240], ... 'Xlim',[0.5,4.5],'YLim', [1, 240]); colorbar(axes1,'Position',... [0.92 0.11 0.01 0.82]);