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Deploy NR HDL Reference Applications on SoCs

These examples show how to implement 5G NR HDL cell search, MIB recovery, and SIB1 recovery on Xilinx®-based platforms by using hardware-software co-design and hardware support packages.

The workflow for designing and deploying a 5G NR cell search, MIB recovery, and SIB1 recovery algorithm to hardware is shown.

There are three examples which demonstrate the final step in the workflow. The first two implement the algorithm up to the MIB recovery step, and the third implements SIB1 recovery.

These examples use hardware-software co-design modeling techniques to implement the algorithm shown in the diagram. They reuse the Simulink® models presented in the NR HDL Cell Search, NR HDL MIB Recovery, and NR HDL SIB1 Recovery examples to generate HDL for the FPGA logic. They then add all of the software modeling and interfacing required to implement the algorithm in real-time on hardware.

For a more detailed description of the algorithm see the NR HDL Downlink Receiver MATLAB Reference example. For a general description of how MATLAB® and Simulink can be used together to develop deployable models, see Wireless Communications Design for FPGAs and ASICs.